dac1408d650 NXP Semiconductors, dac1408d650 Datasheet - Page 42

• Manufacturer Part Number: dac1408d650
• Description: Dual 14-bit Dac, Up To 650 Msps, 2? And 4? Interpolating With Jesd204a Interface
• Manufacturer: NXP Semiconductors

Table 39.
Address Register name
0
1
2
4
5
6
7
8
9
10 0Ah IQ_LEVEL_CNTR
11 0Bh IQ_DC_LEVEL_L
16 10h SET_ICHP_PD1 R/W -
17 11h SET_ICHP_PD2 R/W
18 12h SET_ICHP_PFD R/W
19 13h SET_RATIO_PD1 R/W
20 14h SET_RATIO_PD2 R/W
21 15h SET_RATIO_PFD R/W -
22 16h SET_VCM_VOLT
23 17h SET_SYNC
26 1Ah MISC_CNTRLS
00h MAINCONTROL R/W -
01h MAN_PON
02h MAN_SUPD
04h RST_EXT_FCLK R/W
05h RST_EXT_DCLK R/W
06h DCSMU_PREDIV
07h PLL_CHARGETI
08h PLL_RUN_IN_TI
09h CA_RUN_IN_TIM
CNT
ME
ME
E
L
SB
AGE
10.15.2.3 Page 2 allocation map description
Page 2 register allocation map
R/W Bit definition
R/W -
R/W MAN_PLL
R/W
R/W
R/W
R/W CA_RUNIN_TIME[7:0]
R/W
R/W
R/W
R/W SET_SYNC_VCOM[3:0]
R/W -
b7
_SEL_PD
_LN3
ILEV_CNTRL[1:0]
-
-
-
-
-
b6
-
-
MAN_PLL
_SEL_PD
_LN2
-
-
-
-
-
-
-
-
b5
FULL
RE_INIT
MAN_PON_
CLKBUFFE
R
MAN_PLL_
SEL_PD_LN
1
QLEV_CNTRL[1:0]
-
-
-
-
-
-
-
-
b4
FULL
RE_INIT
MAN_PLL_S
EL_PD_LN0
-
-
-
MAN_PON_
RST_EXT_DCLK_TIME[7:0]
RST_EXT_FCLK_TIME[7:0]
DCSMU PREDIVIDER[7:0]
PLL_CHARGE_TIME[7:0]
ALL
PLL_RUNIN_TIME[7:0]
-
-
-
-
-
IQ_DC_LEVEL[7:0]
b3
MAN_PON_
CNTR
MAN_PON_L
N3
MAN_PLL_S
TARTUP_LN
3
SET_RATIO_PFD[3:0]
SET_SYNC_LEVEL[3:0]
-
-
b2
MAN_SUPD_
CNTR
MAN_PON_L
N2
MAN_PLL_S
TARTUP_LN
2
JD_MODE
SET_RATIO_PD1[3:0]
SET_RATIO_PD2[3:0]
SET_ICHP_PD1[3:0]
SET_ICHP_PD2[3:0]
SET_ICHP_PFD[3:0]
IQ_DC_LEVEL[11:9]
SET_VCM[2:0]
b1
FORCE_RES
ET_DCLK
MAN_PLL_S
TARTUP_LN
1
CDI_MODE
MAN_PON_L
N1
b0
FORCE_RE
SET_FCLK
MAN_PON_
LN0
MAN_PLL_S
TARTUP_LN
0
SR_CDI
Default
Bin
00000011 03h
00000000 00h
00000000 00h
00111111 3Fh
00100000 20h
00011110 1Eh
00110010 32h
00110010 32h
00000100 04h
01011000 58h
00000000 00h
00000001 01h
00000001 01h
00000001 01h
00000010 02h
00001000 08h
00000110 06h
00000010 02h
01000011 43h
00000100 04h
Hex