dac1408d650 NXP Semiconductors, dac1408d650 Datasheet - Page 39
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dac1408d650
Manufacturer Part Number
dac1408d650
Description
Dual 14-bit Dac, Up To 650 Msps, 2? And 4? Interpolating With Jesd204a Interface
Manufacturer
NXP Semiconductors
Datasheet
1.DAC1408D650.pdf
(88 pages)
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Part Number:
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NXP Semiconductors
DAC1408D650_1
Objective data sheet
Table 21.
Default settings are shown highlighted.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Bit
7
6
5
4 to 3 PLL_DIV[1:0]
2 to 1 PLL_PHASE[1:0]
0
Bit
7 to 0 FREQ_NCO[7:0]
Bit
7 to 0 FREQ_NCO[15:8]
Bit
7 to 0 FREQ_NCO[23:16]
Bit
7 to 0 FREQ_NCO[31:24]
Bit
7 to 0 PH_NCO[7:0]
Symbol
PLL_PD
-
PLL_DIV_PD
PLL_POL
Symbol
Symbol
Symbol
Symbol
Symbol
PLLCFG register (address 02h) bit description
FREQNCO_LSB register (address 03h) bit description
FREQNCO_LISB register (address 04h) bit description
FREQNCO_UISB register (address 05h) bit description
FREQNCO_MSB register (address 06h) bit description
PHINCO_LSB register (address 07h) bit description
Rev. 01 — 26 May 2009
Dual 14-bit DAC, up to 650 Msps, 2 and 4 interpolating
Access
R/W
R/W
R/W
R/W
R/W
R/W
Access Value Description
R/W
Access Value Description
R/W
Access Value Description
R/W
Access Value Description
R/W
Access Value Description
R/W
-
-
-
-
-
Value Description
0
1
0
1
00
01
-
00
01
10
0
1
lower 8-bits for the NCO frequency setting
lower intermediate 8-bits for the NCO
frequency setting
upper intermediate 8-bits for the NCO
frequency setting
most significant 8-bits for the NCO frequency
setting
lower 8-bits for the NCO phase setting
PLL
undefined
PLL divider
PLL divider factor
PLL phase shift of f
clock edge of DAC (f
switched on
switched off
switched on
switched off
2
4
8
0
120
240
normal
inverted
DAC1408D650
s
s
)
© NXP B.V. 2009. All rights reserved.
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