dac1408d650 NXP Semiconductors, dac1408d650 Datasheet - Page 21

• Manufacturer Part Number: dac1408d650
• Description: Dual 14-bit Dac, Up To 650 Msps, 2? And 4? Interpolating With Jesd204a Interface
• Manufacturer: NXP Semiconductors

NXP Semiconductors
DAC1408D650_1
Objective data sheet
Fig 9.
RESET_N
(optional)
(optional)
SCS_N
SCLK
SDIO
SDO
R/W indicates the mode access, (see
SPI protocol
10.3.2 SPI timing description
R/W
This interface can be configured as a 3-wire type (SDIO as bidirectional pin) or a 4-wire
type (SDIO and SDO as unidirectional pin, input and output port respectively). In both
configurations, SCLK acts as the serial clock, and SCS_N acts as the serial chip select
bar.
Each read/write operation is sequenced by the SCS_N signal and enabled by a LOW
assertion to drive the chip with 2 bytes to 5 bytes, depending on the content of the
instruction byte (see
Table 8.
In
byte.
Table 9.
A[4:0]: indicates which register is being addressed. In the case of a multiple transfer, this
address concerns the first register after which the next registers follow directly in a
decreasing order according to
The SPI interface can operate at a frequency of up to 15 MHz. The SPI timing is shown in
Figure
R/W
0
1
N1
0
0
1
1
N1
Table 9
N0
10.
below, N1 and N0 indicate the number of bytes transferred after the instruction
Read or Write mode access description
Number of bytes to be transferred
A4
A3
Table
Description
Write mode operation
Read mode operation
Table
N0
0
1
0
1
8):
A2
Rev. 01 — 26 May 2009
9).
A1
Dual 14-bit DAC, up to 650 Msps, 2 and 4 interpolating
Table 18 “Page 0 register allocation
A0
D7
D7
Number of bytes transferred
1
2
3
4
D6
D6
D5
D5
D4
D4
DAC1408D650
D3
D3
D2
D2
map”.
© NXP B.V. 2009. All rights reserved.
D1
D1
D0
D0
001aaj812
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