adsp-2186n Analog Devices, Inc., adsp-2186n Datasheet - Page 12

• Manufacturer Part Number: adsp-2186n
• Description: Dsp Microcomputer
• Manufacturer: Analog Devices, Inc.

ADSP-218xN
IOWAIT0–3 as shown in
the wait state mode bit, specify up to 15 wait states to be auto-
matically generated for each of four regions. The wait states act
on address ranges, as shown in
Note: In Full Memory Mode, all 2048 locations of I/O space are
directly addressable. In Host Memory Mode, only address pin
A0 is available; therefore, additional logic is required externally
to achieve complete addressability of the 2048 I/O
space locations.
Table 6. Wait States
Composite Memory Select
ADSP-218xN series members have a programmable memory
select signal that is useful for generating memory select signals
for memories mapped to more than one space. The CMS signal
is generated to have the same timing as each of the individual
memory select signals (PMS, DMS, BMS, IOMS) but can com-
bine their functionality. Each bit in the CMSSEL register, when
set, causes the CMS signal to be asserted when the selected
memory select is asserted. For example, to use a 32K word
memory to act as both program and data memory, set the PMS
and DMS bits in the CMSSEL register and use the CMS pin to
drive the chip select of the memory, and use either DMS or PMS
as the additional address bit.
The CMS pin functions like the other memory select signals
with the same timing and bus request logic. A 1 in the enable bit
causes the assertion of the CMS signal at the same time as the
selected memory select signal. All enable bits default to 1 at
reset, except the BMS bit.
See
ble flag and composite control register and the system
control register.
Byte Memory Select
The ADSP-218xN’s BMS disable feature combined with the
CMS pin allows use of multiple memories in the byte memory
space. For example, an EPROM could be attached to the BMS
Address Range
0x000–0x1FF
0x200–0x3FF
0x400–0x5FF
0x600–0x7FF
WAIT STATE MODE SELECT
0 = NORMAL MODE (PWAIT, DWAIT, IOWAIT0–3 = N WAIT STATES,
1 = 2N + 1 MODE (PWAIT, DWAIT, IOWAIT0–3 = 2N + 1 WAIT STATES,
Figure 11
RANGING FROM 0 TO 7)
RANGING FROM 0 TO 15)
1 5 1 4 1 3 1 2 1 1 1 0
1
1
DWAIT
1
and
1
Figure 10. Wait State Control Register
IOWAIT3
Figure 12
1
WAIT STATE CONTROL
IOWAIT0 and Wait State Mode Select Bit
IOWAIT1 and Wait State Mode Select Bit
IOWAIT2 and Wait State Mode Select Bit
IOWAIT3 and Wait State Mode Select Bit
1
Wait State Register
9
1
Figure
8
1
IOWAIT2
for illustration of the programma-
7
1
Table
10, which in combination with
6
1
IOWAIT1
5
1
6.
4
1
3
1
2
1
IOWAIT0
1
1
0
Rev. A | Page 12 of 48 | August 2006
1
DM(0x3FFE)
select, and a flash memory could be connected to CMS. Because
at reset BMS is enabled, the EPROM would be used for booting.
After booting, software could disable BMS and set the CMS sig-
nal to respond to BMS, enabling the flash memory.
Byte Memory
The byte memory space is a bidirectional, 8-bit-wide,
external memory space used to store programs and data. Byte
memory is accessed using the BDMA feature. The byte memory
space consists of 256 pages, each of which is 16K
The byte memory space on the ADSP-218xN series supports
read and write operations as well as four different data formats.
The byte memory uses data bits 15–8 for data. The byte mem-
ory uses data bits 23–16 and address bits 13–0 to create a 22-bit
address. This allows up to a 4 megabit
or RAM to be used without glue logic. All byte memory accesses
are timed by the BMWAIT register and the wait state mode bit.
Byte Memory DMA (BDMA, Full Memory Mode)
The byte memory DMA controller
and storing of program instructions and data using the byte
memory space. The BDMA circuit is able to access the byte
memory space while the processor is operating normally and
steals only one DSP cycle per 8-, 16-, or 24-bit word transferred.
SPO RT0 ENABL E
0 = DISABL E
1 = ENABL E
N OTE: RESERVED BITS ARE SHO WN O N A G RAY FIELD . THESE B ITS
15 14 13 12 11 10 9
1
R ESERVED
SPO RT1 C ONF IGURE
0 = FI, FO , IRQ0, IRQ1, SCLK
1 = SPO RT1
B MW AIT
15 14 13 12 11 10 9
SET T O 0
SPORT 1 ENABLE
0 = DISABLE
1 = ENABLE
0
Figure 11. Programmable Flag and Composite Control Register
1
0
PROGRAMMABLE FLAG AND COMPOSITE
SHOUL D ALW AYS BE WR ITTEN W ITH Z EROS.
1
( WH ERE BIT : 11- IOM , 10-B M, 9-DM , 8-PM )
0
1
0
1
0
Figure 12. System Control Register
CM S SEL
0 = DIS ABLE CMS
1 = E NABLE CMS
0
1
SELECT CONTROL
1
SYSTEM CONTROL
RESERVED,ALW AYS
0
8
1
8
0
SET TO 0
7
0
7
0
6
0
DISABLE BMS
0 = ENABL E BMS
1 = DISAB LE BMS
6
0
5
0
5
0
PF TY P E
0 = IN PUT
1 = O UTP UT
(Figure
4
0
4
0
3
0
3
0
8 (32 megabit) ROM
2
0
13) allows loading
PWAIT
PROGRAM MEMOR Y
W AIT ST ATES
2
1
1
0
1
1
0
0
0
1
8 bits.
DM(0x3FE6)
DM(0x3F FF)