adsp-2186n Analog Devices, Inc., adsp-2186n Datasheet - Page 18

• Manufacturer Part Number: adsp-2186n
• Description: Dsp Microcomputer
• Manufacturer: Analog Devices, Inc.

ADSP-218xN
PIN DESCRIPTIONS
ADSP-218xN series members are available in a 100-lead LQFP
package and a 144-ball BGA package. In order to maintain max-
imum functionality and reduce package size and pin count,
some serial port, programmable flag, interrupt and external bus
pins have dual, multiplexed functionality. The external bus pins
are configured during RESET only, while serial port pins are
Table 9. Common-Mode Pins
Pin Name
RESET
BR
BG
BGH
DMS
PMS
IOMS
BMS
CMS
RD
WR
IRQ2
PF7
IRQL1
PF6
IRQL0
PF5
IRQE
PF4
Mode D
PF3
Mode C
PF2
Mode B
PF1
Mode A
PF0
CLKIN
XTAL
CLKOUT
SPORT0
SPORT1
IRQ1–0, FI, FO
PWD
PWDACK
FL0, FL1, FL2
V
V
GND
DDINT
DDEXT
No. of Pins
1
1
1
1
1
1
3
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
5
5
1
2
4
10
I/O
I
I
O
O
O
O
O
O
O
O
O
I
I/O
I
I/O
I
I/O
I
I/O
I
I/O
I
I/O
I
I/O
I
I/O
I
O
O
I/O
I/O
I
O
O
I
I
I
Rev. A | Page 18 of 48 | August 2006
Processor Reset Input
Bus Request Input
Bus Grant Output
Bus Grant Hung Output
Data Memory Select Output
Program Memory Select Output
Memory Select Output
Byte Memory Select Output
Combined Memory Select Output
Memory Read Enable Output
Memory Write Enable Output
Edge- or Level-Sensitive Interrupt Request
Level-Sensitive Interrupt Requests
Level-Sensitive Interrupt Requests
Edge-Sensitive Interrupt Requests
Mode Select Input—Checked Only During RESET
Mode Select Input—Checked Only During RESET
Mode Select Input—Checked Only During RESET
Mode Select Input—Checked Only During RESET
Quartz Crystal Output
Processor Clock Output
Serial Port I/O Pins
Serial Port I/O Pins
Edge- or Level-Sensitive Interrupts, FI, FO
Power-Down Control Input
Power-Down Acknowledge Control Output
Output Flags
Internal V
External V
Function
Programmable I/O Pin
Programmable I/O Pin
Programmable I/O Pin
Programmable I/O Pin
Programmable I/O Pin During Normal Operation
Programmable I/O Pin During Normal Operation
Programmable I/O Pin During Normal Operation
Programmable I/O Pin During Normal Operation
Clock Input
Ground (LQFP)
DD
DD
(1.8 V) Power (LQFP)
(1.8 V, 2.5 V, or 3.3 V) Power (LQFP)
software configurable during program execution. Flag and
interrupt functionality is retained concurrently on multiplexed
pins. In cases where pin functionality is reconfigurable, the
default state is shown in plain text in
functionality is shown in italics.
1
1
1
2
1
Table
9, while alternate