adsp-2186n Analog Devices, Inc., adsp-2186n Datasheet - Page 7

• Manufacturer Part Number: adsp-2186n
• Description: Dsp Microcomputer
• Manufacturer: Analog Devices, Inc.

such as SCLK, CLKOUT, and timer clock, are reduced by the
same ratio. The default form of the instruction, when no clock
divisor is given, is the standard IDLE instruction.
When the IDLE (n) instruction is used, it effectively slows down
the processor’s internal clock and thus its response time to
incoming interrupts. The one-cycle response time of the stan-
dard idle state is increased by n, the clock divisor. When an
enabled interrupt is received, ADSP-218xN series members
remain in the idle state for up to a maximum of n processor
cycles (n = 16, 32, 64, or 128) before resuming nor-
mal operation.
When the IDLE (n) instruction is used in systems that have an
externally generated serial clock (SCLK), the serial clock rate
may be faster than the processor’s reduced internal clock rate.
Under these conditions, interrupts must not be generated at a
1/2
CRYSTAL
SERIAL
DEVICE
SERIAL
DEVICE
OR
CLOCK
FULL MEMORY MODE
MODE C/PF2
MODE A/PF0
MODE B/PF1
CLKIN
XTAL
MODE D/PF3
SCLK1
RFS1 OR IRQ0
TFS1 OR
DT1 OR FO
DR1 OR FI
FL0–2
IRQ2/PF7
IRQE/PF4
IRQL0/PF5
IRQL1/PF6
SCLK0
RFS0
TFS0
DT0
DR0
SPORT0
ADSP-218xN
SPORT1
IRQ1
ADDR13–0
DATA23–0
PWDACK
IOMS
PWD
BGH
BMS
PMS
DMS
CMS
WR
BR
BG
RD
14
24
Rev. A | Page 7 of 48 | August 2006
A13–0
D23–16
D15–8
A10–0
D23–8
A13–0
D23–0
Figure 2. Basic System Interface
A0–A21
DATA
CS
ADDR
DATA
CS
ADDR
DATA
DM SEGMENTS
2048 LOCATIONS
PM SEGMENTS
(PERIPHERALS)
MEMORY
OVERLAY
MEMORY
TWO 8K
I/O SPACE
TWO 8K
BYTE
faster rate than can be serviced, due to the additional time the
processor takes to come out of the idle state (a maximum of n
processor cycles).
SYSTEM INTERFACE
Figure 2
ADSP-218xN series, two serial devices, a byte-wide EPROM,
and optional external program and data overlay memories
(mode-selectable). Programmable wait state generation allows
the processor to connect easily to slow peripheral devices.
ADSP-218xN series members also provide four external inter-
rupts and two serial ports or six external interrupts and one
serial port. Host Memory Mode allows access to the full external
data bus, but limits addressing to a single address bit (A0).
Through the use of external hardware, additional system
peripherals can be added in this mode to generate and latch
address signals.
µCONTROLLER
shows typical basic system configurations with the
INTERFACE
1/2
SYSTEM
CRYSTAL
OR
OR
DEVICE
SERIAL
SERIAL
DEVICE
CLOCK
16
HOST MEMORY MODE
CLKIN
IRQ2/PF7
IRQL1/PF6
MODE D/PF3
MODE C/PF2
MODE A/PF0
MODE B/PF1
XTAL
FL0–2
IRQE/PF4
IRQL0/PF5
SCLK1
RFS1 OR IRQ0
TFS1 OR IRQ1
DT1 OR FO
DR1 OR FI
SCLK0
RFS0
TFS0
DT0
DR0
IRD/D6
IWR/D7
IACK/D3
IDMA PORT
IS/D4
IAL/D5
IAD15-0
SPORT0
SPORT1
ADSP-218xN
DATA23–8
PWDACK
IOMS
BMS
DMS
CMS
BGH
PWD
PMS
WR
RD
BR
BG
A0
ADSP-218xN
1
16