adsp-2186n Analog Devices, Inc., adsp-2186n Datasheet - Page 4

• Manufacturer Part Number: adsp-2186n
• Description: Dsp Microcomputer
• Manufacturer: Analog Devices, Inc.

ADSP-218xN
The two address buses (PMA and DMA) share a single external
address bus, allowing memory to be expanded off-chip, and the
two data buses (PMD and DMD) share a single external data
bus. Byte memory space and I/O memory space also share the
external buses.
Program memory can store both instructions and data, permit-
ting ADSP-218xN series members to fetch two operands in a
single cycle, one from program memory and one from data
memory. ADSP-218xN series members can fetch an operand
from program memory and the next instruction in the
same cycle.
In lieu of the address and data bus for external memory connec-
tion, ADSP-218xN series members may be configured for 16-bit
Internal DMA port (IDMA port) connection to external sys-
tems. The IDMA port is made up of 16 data/address pins and
five control pins. The IDMA port provides transparent, direct
access to the DSP’s on-chip program and data RAM.
An interface to low-cost byte-wide memory is provided by the
Byte DMA port (BDMA port). The BDMA port is bidirectional
and can directly address up to four megabytes of external RAM
or ROM for off-chip storage of program overlays or data tables.
The byte memory and I/O memory space interface supports
slow memories and I/O memory-mapped peripherals with pro-
grammable wait state generation. External devices can gain
control of external buses with bus request/grant signals (BR,
BGH, and BG). One execution mode (Go Mode) allows the
ADSP-218xN to continue running from on-chip memory. Nor-
mal execution mode requires the processor to halt while buses
are granted.
ADSP-218xN series members can respond to eleven interrupts.
There can be up to six external interrupts (one edge-sensitive,
two level-sensitive, and three configurable) and seven internal
interrupts generated by the timer, the serial ports (SPORT), the
BDMA port, and the power-down circuitry. There is also a mas-
ter RESET signal. The two serial ports provide a complete
synchronous serial interface with optional companding in hard-
ware and a wide variety of framed or frameless data transmit
and receive modes of operation.
Each port can generate an internal programmable serial clock or
accept an external serial clock.
ADSP-218xN series members provide up to 13 general-purpose
flag pins. The data input and output pins on SPORT1 can be
alternatively configured as an input flag and an output flag. In
addition, eight flags are programmable as inputs or outputs, and
three flags are always outputs.
A programmable interval timer generates periodic interrupts. A
16-bit count register (TCOUNT) decrements every n processor
cycle, where n is a scaling value stored in an 8-bit register
(TSCALE). When the value of the count register reaches zero,
an interrupt is generated and the count register is reloaded from
a 16-bit period register (TPERIOD).
Rev. A | Page 4 of 48 | August 2006
Serial Ports
ADSP-218xN series members incorporate two complete syn-
chronous serial ports (SPORT0 and SPORT1) for serial
communications and multiprocessor communication.
Following is a brief list of the capabilities of the ADSP-218xN
SPORTs. For additional information on Serial Ports, refer to the
ADSP-218x DSP Hardware Reference.
• SPORTs are bidirectional and have a separate, double-
• SPORTs can use an external serial clock or generate their
• SPORTs have independent framing for the receive and
• SPORTs support serial data word lengths from 3 bits to
• SPORT receive and transmit sections can generate unique
• SPORTs can receive and transmit an entire circular buffer
• SPORT0 has a multichannel interface to selectively receive
• SPORT1 can be configured to have two external interrupts
buffered transmit and receive section.
own serial clock internally.
transmit sections. Sections run in a frameless mode or with
frame synchronization signals internally or externally gen-
erated. Frame sync signals are active high or inverted, with
either of two pulsewidths and timings.
16 bits and provide optional A-law and μ-law companding,
according to CCITT recommendation G.711.
interrupts on completing a data word transfer.
of data with only one overhead cycle per data word. An
interrupt is generated after a data buffer transfer.
and transmit a 24 word or 32-word, time-division multi-
plexed, serial bitstream.
(IRQ0 and IRQ1) and the FI and FO signals. The internally
generated serial clock may still be used in this
configuration.