adsp-2186n Analog Devices, Inc., adsp-2186n Datasheet - Page 30

• Manufacturer Part Number: adsp-2186n
• Description: Dsp Microcomputer
• Manufacturer: Analog Devices, Inc.

ADSP-218xN
Bus Request–Bus Grant
Table 17. Bus Request–Bus Grant
1
2
3
Parameter
Timing Requirements:
t
t
Switching Characteristics:
t
t
t
t
t
t
BR is an asynchronous signal. If BR meets the setup/hold requirements, it will be recognized during the current clock cycle; otherwise the signal will be recognized on
xMS = PMS, DMS, CMS, IOMS, BMS.
BGH is asserted when the bus is granted and the processor or BDMA requires control of the bus to continue.
BH
BS
SD
SDB
SE
SEC
SDBH
SEH
the following cycle. Refer to the ADSP-2100 Family User’s Manual for BR/BG cycle relationships.
BR Hold after CLKOUT High
BR Setup before CLKOUT Low
CLKOUT High to xMS, RD, WR Disable
xMS, RD, WR Disable to BG Low
BG High to xMS, RD, WR Enable
xMS, RD, WR Enable to CLKOUT High
xMS, RD, WR Disable to BGH Low
BGH High to xMS, RD, WR Enable
PMS, DMS
CMS, WR,
BMS, RD
CLKOUT
CLKOUT
IOMS
BGH
BG
BR
1
1
3
3
t
Rev. A | Page 30 of 48 | August 2006
SD
t
Figure 28. Bus Request–Bus Grant
BH
2
t
t
BS
t
SDBH
SDB
Min
0.25t
0.25t
0
0
0.25t
0
0
t
t
SEH
SE
CK
CK
CK
t
+ 2
+ 8
– 3
SEC
Max
0.25t
CK
+ 8
Unit
ns
ns
ns
ns
ns
ns
ns
ns