adsp-2165ks-80 Analog Devices, Inc., adsp-2165ks-80 Datasheet - Page 22

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adsp-2165ks-80

Manufacturer Part Number
adsp-2165ks-80
Description
Dsp Microcomputers With Rom
Manufacturer
Analog Devices, Inc.
Datasheet
ADSP-216x
TIMING PARAMETERS (ADSP-2161/ADSP-2163/ADSP-2165)
CLOCK SIGNALS AND RESET
Parameter
Timing Requirements:
t
t
t
t
Switching Characteristics:
t
t
t
NOTES
1
2
Applies after power-up sequence is complete. Internal phase lock loop requires no more than 2000 CLKIN cycles, assuming stable CLKIN (not including crystal
For 25 MHz only, the maximum frequency dependency for t
CK
CKL
CKH
RSP
CPL
CPH
CKOH
oscillator startup time).
CLKIN Period
CLKIN Width Low
CLKIN Width High
RESET Width Low
CLKOUT Width Low
CLKOUT Width High
CLKIN High to CLKOUT High
CLKOUT
CLKIN
Min
60
20
20
300
20
20
0
16.67 MHz
CKOH
Max
150
20
Figure 21. Clock Signals
= 15 ns.
t
CKL
t
CPL
t
CK
Min
50
20
20
250
15
15
0
–22–
20 MHz
t
CKH
Max
150
20
t
t
CHOK
CPH
Min
40
15
15
200
10
10
0
25 MHz
Max
150
15
2
Frequency Dependency
Min
t
20
20
5t
0.5t
0.5t
0
CK
CK
CK
CK
1
– 10
– 10
Max
150
20
2
REV. 0
Unit
ns
ns
ns
ns
ns
ns
ns

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