adsp-2165ks-80 Analog Devices, Inc., adsp-2165ks-80 Datasheet - Page 24

• Manufacturer Part Number: adsp-2165ks-80
• Description: Dsp Microcomputers With Rom
• Manufacturer: Analog Devices, Inc.

ADSP-216x
TIMING PARAMETERS (ADSP-2161/ADSP-2163/ADSP-2165)
BUS REQUEST/BUS GRANT
Parameter
Timing Requirements:
t
t
Switching Characteristics:
t
t
t
t
NOTES
1
2
Section 10.2.4, “Bus Request/Grant,” on page 212 of the ADSP-2100 Family User’s Manual, Third Edition, states that “When BR is recognized, the processor responds
immediately by asserting BG during the same cycle.” This is incorrect for the current versions of all ADSP-21xx processors: BG is asserted in the cycle after BR is
recognized. No external synchronization circuit is needed when BR is generated as an asynchronous signal.
If BR meets the t
For 25 MHz only, the minimum frequency dependency formula for t
BH
BS
SD
SDB
SE
SEC
a pulsewidth greater than 10 ns.
BR Hold After CLKOUT High
BR Setup Before CLKOUT Low
CLKOUT High to DMS,
PMS, BMS, RD, WR Disable
DMS, PMS, BMS, RD, WR
Disable to BG Low
BG High to DMS, PMS,
BMS, RD, WR Enable
DMS, PMS, BMS, RD, WR
Enable to CLKOUT High
BS
and t
BH
setup/hold requirements, it will be recognized in the current processor cycle; otherwise it is recognized in the following cycle. BR requires
PMS, DMS
CLKOUT
CLKOUT
BMS, RD
WR
BR
BG
1
1
Min
20
35
0
0
5
16.67 MHz
t
Figure 23. Bus Request/Bus Grant
SD
t
BH
t
BS
t
SDB
Max
35
SEC
= (0.25t
Min
17.5
32.5
0
0
2.5
–24–
20 MHz
CK
– 8.5).
Max
32.5
Min
15
30
0
0
1.5
25 MHz
2
t
Max
30
SE
t
SEC
Frequency Dependency
Min
0.25t
0.25t
0
0
0.25t
CK
CK
CK
+ 5
+ 20
– 10
2
Max
0.25t
CK
+ 20
REV. 0
Unit
ns
ns
ns
ns
ns
ns