adsp-2165ks-80 Analog Devices, Inc., adsp-2165ks-80 Datasheet - Page 8

• Manufacturer Part Number: adsp-2165ks-80
• Description: Dsp Microcomputers With Rom
• Manufacturer: Analog Devices, Inc.

ADSP-216x
ADSP-2163/ADSP-2164
When MMAP = 0, on-chip program memory ROM occupies
4K words beginning at address 0x0000. Off-chip program
memory uses the remaining 12K words beginning at address
0x1000.
When MMAP = 1, 2K words of off-chip program memory begin
at address 0x0000. 2K words of on-chip program memory ROM
is at 0x0800 to 0x0FF0, and the remainder 2K words of pro-
gram memory ROM is at 0x3800 to 0x3FFF. An additional
10K of off-chip program memory is at 0x1000 to 0x37FF.
Data Memory Interface
The data memory address bus (DMA) is 14 bits wide. The
bidirectional external data bus is 24 bits wide, with the upper 16
bits used for data memory data (DMD) transfers.
The data memory select (DMS) signal indicates access to data
memory and can be used as a chip select signal. The write (WR)
signal indicates a write operation and can be used as a write
strobe. The read (RD) signal indicates a read operation and can
be used as a read strobe or output enable signal.
The ADSP-216x processors support memory-mapped I/O, with
the peripherals memory-mapped into the data memory address
space and accessed by the processor in the same manner as data
memory.
Data Memory Map
For the ADSP-2165/ADSP-2166, on-chip data memory RAM
resides in the 4K words beginning at address 0x2000, as shown
in Figure 7. Data memory locations from 0x3000 to the end of
data memory at 0x3FFF are reserved. Control and status regis-
ters for the system, timer, wait-state configuration, and serial port
operations are located in this region of memory.
The remaining 8K of data memory is located off-chip. This
external data memory is divided into three zones, each associ-
ated with its own wait-state generator. This allows slower pe-
ripherals to be memory-mapped into data memory for which
wait states are specified. By mapping peripherals into different
zones, you can accommodate peripherals with different wait-
state requirements. All zones default to 7 wait states after
RESET.
Figure 6. ADSP-2163/ADSP-2164 Program Memory Maps
MMAP = 0
RESERVED
EXTERNAL
INTERNAL
ROM
12K
4K
0x0000
0x0FF0
0x0FFF
0x1000
0x3FFF
MMAP = 1
EXTERNAL
RESERVED
EXTERNAL
INTERNAL
INTERNAL
ROM
ROM
10K
2K
2K
2K
0x0000
0x07FF
0x0800
0x0FF0
0x0FFF
0x1000
0x37FF
0x3800
0x3FFF
–8–
ADSP-2161/ADSP-2162/ADSP-2163/ADSP-2164
For the ADSP-2161/ADSP-2162/ADSP-2163/ADSP-2164, on-
chip data memory RAM resides in the 512 words beginning at
address 0x3800, also shown in Figure 8. Data memory locations
from 0x3A00 to the end of data memory at 0x3FFF are reserved.
Control and status registers for the system, timer, wait-state
configuration, and serial port operations are located in this
region of memory.
Figure 8. ADSP-2161/ADSP-2162/ADSP-2163/ADSP-2164
Data Memory Map
The remaining 14K of data memory is located off-chip. This
external data memory is divided into five zones, each associated
with its own wait-state generator. This allows slower peripherals
to be memory-mapped into data memory for which wait states
are specified. By mapping peripherals into different zones, you
can accommodate peripherals with different wait-state require-
ments. All zones default to seven wait states after RESET.
Figure 7. ADSP-2165/ADSP-2166 Data Memory Map
EXTERNAL
INTERNAL
RAM
RAM
CONTROL REGISTERS
ADSP-2161/62/63/64
MEMORY-MAPPED
10K EXTERNAL
1K EXTERNAL
1K EXTERNAL
1K EXTERNAL
1K EXTERNAL
& RESERVED
DWAIT0
DWAIT1
DWAIT2
DWAIT3
DWAIT4
512
4K
MEMORY-MAPPED
1K EXTERNAL
1K EXTERNAL
6K EXTERNAL
& RESERVED
REGISTERS
DWAIT0
DWAIT1
DWAIT2
16 INTERNAL
4K
ADDRESS (HEX)
16
0x0000
0x0400
0x0800
0x3000
0x3400
0x3800
0x3A00
0x3C00
0x3FFF
ADDRESS (HEX)
EXTERNAL
INTERNAL
0x0000
0x0400
0x0800
0x2000
0x3000
0x3FFF
RAM
RAM
REV. 0