adsp-2165ks-80 Analog Devices, Inc., adsp-2165ks-80 Datasheet - Page 29

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adsp-2165ks-80

Manufacturer Part Number
adsp-2165ks-80
Description
Dsp Microcomputers With Rom
Manufacturer
Analog Devices, Inc.
Datasheet
TIMING PARAMETERS (ADSP-2162/ADSP-2164/ADSP-2166)
CLOCK SIGNALS AND RESET
Parameter
Timing Requirements:
t
t
t
t
Switching Characteristics:
t
t
t
NOTE
1
REV. 0
Applies after power-up sequence is complete. Internal phase lock loop requires no more than 2000 CLKIN cycles assuming stable CLKIN (not including crystal
CK
CKL
CKH
RSP
CPL
CPH
CKOH
oscillator startup time).
CLKIN Period
CLKIN Width Low
CLKIN Width High
RESET Width Low
CLKOUT Width Low
CLKOUT Width High
CLKIN High to CLKOUT High
CLKOUT
CLKIN
Min
97.6
20
20
488
38.8
38.8
0
10.24 MHz
Figure 27. Clock Signals
Max
150
20
t
CKL
t
CPL
t
CK
–29–
Min
76.9
20
20
384.5
28.5
28.5
0
13.0 MHz
t
CKH
t
t
CHOK
CPH
Max
150
20
Min
60.0
20
20
300
20
20
0
16.67 MHz
Max
150
20
t
20
20
5t
0.5t
0.5t
0
Min
CK
CK
Dependency
Frequency
CK
CK
1
ADSP-216x
– 10
– 10
Max
150
20
Unit
ns
ns
ns
ns
ns
ns
ns

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