adsp-21266skstz-2b Analog Devices, Inc., adsp-21266skstz-2b Datasheet - Page 20

• Manufacturer Part Number: adsp-21266skstz-2b
• Description: Sharc Embedded Processor
• Manufacturer: Analog Devices, Inc.

ADSP-21261/ADSP-21262/ADSP-21266
Clock Input
See
Table 16. Clock Input
1
2
3
4
5
6
Clock Signals
The ADSP-2126x can use an external clock or a crystal. See
CLKIN pin description. The programmer can configure the
ADSP-2126x to use its internal clock generator by connecting
the necessary components to CLKIN and XTAL.
the component connections used for a crystal operating in fun­
damental mode. Note that the 200 MHz clock rate is achieved
using a 12.5 MHz crystal and a PLL multiplier ratio 16:1
(CCLK:CLKIN).
Parameter
Timing Requirements
t
t
t
t
f
t
Applies to all 150 MHz models. See
Applies to all 200 MHz models. See
Applies only for CLK_CFG1–0 = 00 and default values for PLL control bits in PMCTL.
Applies only for CLK_CFG1–0 = 01 and default values for PLL control bits in PMCTL.
See
Any changes to PLL control bits in the PMCTL register must meet core clock timing specification t
CK
CKL
CKH
CKRF
vco
CCLK
NOTE: C1 AND C2 ARE SPECIFIC TO CRYSTAL SPECIFIED FOR X1.
CONTACT CRYSTAL MANUFACTURER FOR DETAILS. CRYSTAL
SELECTION MUST COMPLY WITH CLKCFG1-0 = 10 OR = 01.
CLKIN
Table 16
5
Figure 5 on Page 18
Figure 8. 150 MHz or 200 MHz Operation with a 12.5 MHz
C1
CLKIN
CLKIN Period
CLKIN Width Low
CLKIN Width High
CLKIN Rise/Fall (0.4 V to 2.0 V)
VCO Frequency
CCLK Period
and
Figure
for VCO diagram.
Fundamental Mode Crystal
1M �
X1
Figure 7. Clock Input
6
t
7.
CKH
Ordering Guide on Page
Ordering Guide on Page
C2
XTAL
t
CK
t
CKL
Figure 8
47.
47.
Rev. E | Page 20 of 48 | July 2008
Min
20
7.5
7.5
200
6.66
3
3
3
shows
150 MHz
3
Max
160
80
80
800
10
4
4
4
1
CCLK
.
Min
15
6
6
200
5
3
3
3
200 MHz
Max
3
160
80
80
800
10
4
4
4
2
Unit
ns
ns
ns
ns
MHz
ns