adsp-21266skstz-2b Analog Devices, Inc., adsp-21266skstz-2b Datasheet - Page 28

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adsp-21266skstz-2b

Manufacturer Part Number
adsp-21266skstz-2b
Description
Sharc Embedded Processor
Manufacturer
Analog Devices, Inc.
Datasheet

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ADSP-21261/ADSP-21262/ADSP-21266
Table 26. 16-Bit Memory Read Cycle
1
Parameter
Timing Requirements
t
t
Switching Characteristics
t
t
t
t
t
t
D = (The value set by the PPDUR Bits (5–1) in the PPCTL register) × t
H = t
On reset, ALE is an active high cycle. However, it can be reconfigured by software to be active low.
DRS
DRH
ALEW
ALERW
ADAS
ADAH
ALEHZ
RW
1
1
1
CCLK
(if a hold cycle is specified, else H = 0)
Address/Data 15–0 Setup Before RD high
Address/Data 15–0 Hold After RD high
ALE Pulse Width
ALE Deasserted to Read/Write Asserted
Address/Data 15–0 Setup Before ALE Deasserted
Address/Data 15–0 Hold After ALE Deaserted
ALE Deasserted to Address/Data 15–0 in High-Z
RD Pulse Width
AD15-0
ALE
WR
RD
VALID ADDRESS
t
ADAS
t
ALEW
Figure 18. 16-Bit Memory Read Cycle
Rev. E | Page 28 of 48 | July 2008
t
ADAH
t
t
ALERW
ALEHZ
CCLK
t
RW
t
VALID DATA
DRS
Min
3.3
0
2 × t
1 × t
2.5 × t
0.5 × t
0.5 × t
D – 2
CCLK
CCLK
CCLK
CCLK
CCLK
t
DRH
– 2
– 0.5
– 2.0
– 0.8
– 0.8
Max
0.5 × t
CCLK
+ 2.0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns

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