adsp-21266skstz-2b Analog Devices, Inc., adsp-21266skstz-2b Datasheet - Page 8

• Manufacturer Part Number: adsp-21266skstz-2b
• Description: Sharc Embedded Processor
• Manufacturer: Analog Devices, Inc.

ADSP-21261/ADSP-21262/ADSP-21266
Connections are made using the signal routing unit (SRU,
shown in the block diagram
The SRU is a matrix routing unit (or group of multiplexers) that
enables the peripherals provided by the DAI to be intercon­
nected under software control. This allows easy use of the DAI
associated peripherals for a much wider variety of applications
by using a larger set of algorithms than is possible with noncon­
figurable signal paths.
The DAI also includes six serial ports, two precision clock gen­
erators (PCGs), an input data port (IDP), six flag outputs and
six flag inputs, and three timers. The IDP provides an additional
input path to the ADSP-2126x core, configurable as either eight
channels of I
20-bit wide synchronous parallel data acquisition port. Each
data channel has its own DMA channel that is independent
from the ADSP-2126x’s serial ports.
For complete information on using the DAI, see the
ADSP-2126x SHARC DSP Peripherals Manual.
Serial Ports
The ADSP-2126x features six full duplex synchronous serial
ports that provide an inexpensive interface to a wide variety of
digital and mixed-signal peripheral devices such as the Analog
Devices AD183x family of audio codecs, ADCs, and DACs. The
serial ports are made up of two data lines, a clock, and frame
sync. The data lines can be programmed to either transmit or
receive and each data line has its own dedicated DMA channel.
Serial ports are enabled via 12 programmable and simultaneous
receive or transmit pins that support up to 24 transmit or 24
receive channels of audio data when all six SPORTs are enabled,
or six full duplex TDM streams of 128 channels per frame.
The serial ports operate at up to one-quarter of the DSP core
clock rate, providing each with a maximum data rate of
50M bits/sec for a 200 MHz core and 37.5M bits/sec for a
150 MHz core. Serial port data can be automatically transferred
to and from on-chip memory via a dedicated DMA. Each of the
serial ports can work in conjunction with another serial port to
provide TDM support. One SPORT provides two transmit sig­
nals while the other SPORT provides two receive signals. The
frame sync and clock are shared.
Serial ports operate in four modes:
Left-justified sample pair mode is a mode where in each frame
sync cycle, two samples of data are transmitted/received—one
sample on the high segment of the frame sync, the other on the
low segment of the frame sync. Programs have control over var­
ious attributes of this mode.
Each of the serial ports supports the left-justified sample-pair
and I
monly used by audio codecs, ADCs, and DACs) with two data
pins, allowing four left-justified sample-pair or I
• Standard DSP serial mode
• Multichannel (TDM) mode
• I
• Left-justified sample pair mode
2
2
S protocols (I
S mode
2
S or serial data, or as seven channels plus a single
2
S is an industry-standard interface com­
on Page
1).
2
S channels
Rev. E | Page 8 of 48 | July 2008
(using two stereo devices) per serial port with a maximum of up
to 24 audio channels. The serial ports permit little-endian or
big-endian transmission formats and word lengths selectable
from 3 bits to 32 bits. For the left-justified sample pair and I
modes, data-word lengths are selectable between 8 bits and 32
bits. Serial ports offer selectable synchronization and transmit
modes as well as optional μ-law or A-law companding selection
on a per channel basis. Serial port clocks and frame syncs can be
internally or externally generated.
Serial Peripheral (Compatible) Interface
The serial peripheral interface is an industry-standard synchro­
nous serial link, enabling the ADSP-2126x SPI-compatible port
to communicate with other SPI-compatible devices. SPI is an
interface consisting of two data pins, one device select pin, and
one clock pin. It is a full-duplex synchronous serial interface,
supporting both master and slave modes. The SPI port can
operate in a multimaster environment by interfacing with up to
four other SPI-compatible devices, either acting as a master or
slave device. The ADSP-2126x SPI-compatible peripheral
implementation also features programmable baud rates at up to
50 MHz for a core clock of 200 MHz and up to 37.5 MHz for a
core clock of 150 MHz, clock phases, and polarities. The
ADSP-2126x SPI-compatible port uses open-drain drivers to
support a multimaster configuration and to avoid data
contention.
Parallel Port
The parallel port provides interfaces to SRAM and peripheral
devices. The multiplexed address and data pins (AD15–0) can
access 8-bit devices with up to 24 bits of address, or 16-bit
devices with up to 16 bits of address. In either mode, 8- or 16­
bit, the maximum data transfer rate is one-third the core clock
speed. As an example, a clock rate of 200 MHz is equivalent to
66M byte/sec, and a clock rate of 150 MHz is equivalent to
50M byte/sec.
DMA transfers are used to move data to and from internal
memory. Access to the core is also facilitated through the paral­
lel port register read/write functions. The RD, WR, and ALE
(address latch enable) pins are the control pins for the
parallel port.
Timers
The ADSP-2126x has a total of four timers: a core timer able to
generate periodic software interrupts, and three general-pur­
pose timers that can generate periodic interrupts and be
independently set to operate in one of three modes:
The core timer can be configured to use FLAG3 as a timer
expired output signal, and each general-purpose timer has one
bidirectional pin and four registers that implement its mode of
operation: a 6-bit configuration register, a 32-bit count register,
• Pulse waveform generation mode
• Pulse width count/capture mode
• External event watchdog mode
2
S