adsp-21266skstz-2b Analog Devices, Inc., adsp-21266skstz-2b Datasheet - Page 9

• Manufacturer Part Number: adsp-21266skstz-2b
• Description: Sharc Embedded Processor
• Manufacturer: Analog Devices, Inc.

a 32-bit period register, and a 32-bit pulse width register. A sin­
gle control and status register enables or disables all three
general-purpose timers independently.
ROM-Based Security
The ADSP-2126x has a ROM security feature that provides
hardware support for securing user software code by preventing
unauthorized reading from the internal code when enabled.
When using this feature, the DSP does not boot-load any exter­
nal code, executing exclusively from internal SRAM/ROM.
Additionally, the DSP is not freely accessible via the JTAG port.
Instead, a unique 64-bit key, which must be scanned in through
the JTAG or test access port, will be assigned to each customer.
The device will ignore a wrong key. Emulation features and
external boot modes are only available after the correct key is
scanned.
Program Booting
The internal memory of the ADSP-2126x boots at system
power-up from an 8-bit EPROM via the parallel port, an SPI
master, an SPI slave, or an internal boot. Booting is determined
by the boot configuration (BOOT_CFG1–0) pins.
Phase-Locked Loop
The ADSP-2126x uses an on-chip phase-locked loop (PLL) to
generate the internal clock for the core. On power-up, the
CLK_CFG1–0 pins are used to select ratios of 16:1, 8:1, and 3:1.
After booting, numerous other ratios can be selected via soft­
ware control. The ratios are made up of software configurable
numerator values from 1 to 64 and software configurable divi­
sor values of 2, 4, 8, and 16.
Power Supplies
The ADSP-2126x has separate power supply connections for the
internal (V
power supplies. The internal and analog supplies must meet the
1.2 V requirement. The external supply must meet the 3.3 V
requirement. All external supply pins must be connected to the
same power supply.
Note that the analog supply pin (A
ADSP-2126x’s internal clock generator PLL. To produce a stable
clock, it is recommended that PCB designs use an external filter
circuit for the A
possible to the A
Figure
BLM18AG102SN1D). To reduce noise coupling, the PCB
should use a parallel pair of power and ground planes for
V
itors to the analog power (A
that the A
the processor and not the analog ground plane on the board—
the A
the chip.
TARGET BOARD JTAG EMULATOR CONNECTOR
Analog Devices DSP Tools product line of JTAG emulators uses
the IEEE 1149.1 JTAG test access port of the ADSP-2126x pro­
cessor to monitor and control the target board processor during
DDINT
VSS
3. (A recommended ferrite chip is the muRata
and GND. Use wide traces to connect the bypass capac­
pin should connect directly to digital ground (GND) at
VDD
DDINT
and A
), external (V
VDD
VDD
pin. Place the filter components as close as
/A
VSS
VSS
pins specified in
pins. For an example circuit, see
VDD
DDEXT
) and ground (A
), and analog (A
VDD
) powers the
Figure 3
VSS
VDD
are inputs to
) pins. Note
/A
Rev. E | Page 9 of 48 | July 2008
VSS
)
emulation. Analog Devices DSP Tools product line of JTAG
emulators provides emulation at full processor speed, allowing
inspection and modification of memory, registers, and proces­
sor stacks. The processor’s JTAG interface ensures that the
emulator will not affect target system loading or timing.
For complete information on Analog Devices SHARC DSP
Tools product line of JTAG emulator operation, see the appro­
priate emulator hardware user’s guide.
DEVELOPMENT TOOLS
The ADSP-2126x is supported by a complete automotive refer­
ence design and development board as well as by a complete
home audio reference design board available from Analog
Devices. These boards implement complete audio decoding and
postprocessing algorithms that are factory programmed into the
ROM space of the ADSP-2126x. SIMD optimized libraries con­
sume less processing resources, which results in more available
processing power for custom proprietary features.
The nonvolatile memory of the ADSP-2126x can be configured
to contain a combination of Dolby Digital, Dolby Pro Logic,
Dolby Pro Logic II, Dolby Pro Logic IIx, DTSES, DTS 96/24,
and Neo:6. Multiple S/PDIF and analog I/Os are provided to
maximize end system flexibility.
The ADSP-2126x is also supported with a complete set of
CROSSCORE
including Analog Devices emulators and VisualDSP++
development environment. The same emulator hardware that
supports other SHARC processors also fully emulates the
ADSP-2126x.
The VisualDSP++ project management environment lets pro­
grammers develop and debug an application. This environment
includes an easy to use assembler (which is based on an alge­
braic syntax), an archiver (librarian/library builder), a linker, a
loader, a cycle-accurate instruction-level simulator, a C/C++
compiler, and a C/C++ runtime library that includes DSP and
mathematical functions. A key point for these tools is C/C++
code efficiency. The compiler has been developed for efficient
translation of C/C++ code to DSP assembly. The ADSP-2126x
SHARC DSP has architectural features that improve the
efficiency of compiled C/C++ code.
†
‡
ADSP-21261/ADSP-21262/ADSP-21266
CROSSCORE is a registered trademark of Analog Devices, Inc.
VisualDSP++ is a registered trademark of Analog Devices, Inc.
V DDINT
HIGH-Z FERRITE
BEAD CHIP
®†
software and hardware development tools,
Figure 3. Analog Power Filter Circuit
CLOSE TO A VDD AND A VSS PINS
100nF
LOCATE ALL COMPONENTS
10nF
1nF
ADSP-212xx
A VDD
A VSS
®‡