adsp-21266skstz-2b Analog Devices, Inc., adsp-21266skstz-2b Datasheet - Page 4

• Manufacturer Part Number: adsp-21266skstz-2b
• Description: Sharc Embedded Processor
• Manufacturer: Analog Devices, Inc.

ADSP-21261/ADSP-21262/ADSP-21266
GENERAL DESCRIPTION
The ADSP-21261/ADSP-21262/ADSP-21266 SHARC
are members of the SIMD SHARC family of DSPs featuring
Analog Devices Inc., Super Harvard Architecture. The
ADSP-2126x is source code compatible with the ADSP-21160
and ADSP-21161 DSPs as well as with first generation ADSP­
2106x SHARC processors in SISD (single-instruction, single-
data) mode. Like other SHARC DSPs, the ADSP-2126x are
32-bit/40-bit floating-point processors optimized for high per­
formance audio applications with dual-ported on-chip SRAM,
mask-programmable ROM, multiple internal buses to eliminate
I/O bottlenecks, and an innovative digital audio interface.
Table 1
ning at 200 MHz.
product offerings.
Table 1. Processor Benchmarks (at 200 MHz)
1
As shown in the functional block diagram in
the ADSP-2126x uses two computational units to deliver a 5 to
10 times performance increase over previous SHARC proces­
sors on a range of DSP algorithms. Fabricated in a state-of-the­
art, high speed, CMOS process, the ADSP-2126x DSPs achieve
an instruction cycle time of 5 ns at 200 MHz or 6.6 ns at
150 MHz. With its SIMD computational hardware, the
ADSP-2126x can perform 1200 MFLOPS running at 200 MHz,
or 900 MFLOPS running at 150 MHz.
Table 2. ADSP-2126x SHARC Processor Features
1
Feature
RAM
ROM
Audio Decoders
in ROM
DMA Channels
SPORTs
Package
Benchmark Algorithm
1024 Point Complex FFT (Radix 4, with reversal)
FIR Filter (per tap)
IIR Filter (per biquad)
Matrix Multiply (pipelined)
Divide (y/x)
Inverse Square Root
Assumes two files in multichannel SIMD mode.
For information on available audio decoding algorithms, see
[3×3] × [3×1]
[4×4] × [4×1]
1
shows performance benchmarks for the processors run­
Table 2
1
ADSP-21261
1M bit
3M bit
No
18
4
136-ball BGA
144-lead LQFP
1
shows the features of the individual
ADSP-21262 ADSP-21266
2M bit
4M bit
No
22
6
136-ball BGA
144-lead LQFP
Figure 1 on Page
Table 3 on Page
Speed
(at 200 MHz)
61.3 μs
3.3 ns
13.3 ns
30 ns
53.3 ns
20 ns
30 ns
2M bit
4M bit
Yes
6
136-ball BGA
144-lead LQFP
22
Rev. E | Page 4 of 48 | July 2008
®
DSPs
1,
6.
The ADSP-2126x continues SHARC’s industry-leading stan­
dards of integration for DSPs, combining a high performance
32-bit DSP core with integrated, on-chip system features. These
features include 2M bit dual-ported SRAM memory, 4M bit
dual-ported ROM, an I/O processor that supports 22 DMA
channels, six serial ports, an SPI interface, external parallel bus,
and digital audio interface.
The block diagram of the ADSP-2126x
following architectural features:
Figure 2
precision clock generator to interface with an I
I
would generate itself. Many other SRU configurations are
possible.
FAMILY CORE ARCHITECTURE
The ADSP-2126x is code compatible at the assembly level with
the ADSP-2136x and ADSP-2116x, and with the first generation
ADSP-2106x SHARC DSPs. The ADSP-2126x shares architec­
tural features with the ADSP-2136x and ADSP-2116x SIMD
SHARC family of DSPs, as detailed in the following sections.
SIMD Computational Engine
The ADSP-2126x contain two computational processing ele­
ments that operate as a single-instruction multiple-data (SIMD)
engine. The processing elements are referred to as PEX and PEY
2
S DAC with a much lower jitter clock than the serial port
• Two processing elements, each containing an ALU, multi­
• Data address generators (DAG1, DAG2)
• Program sequencer with instruction cache
• PM and DM buses capable of supporting four 32-bit data
• Three programmable interval timers with PWM genera­
• On-chip dual-ported SRAM (up to 2M bit)
• On-chip dual-ported, mask-programmable ROM
• JTAG test access port
• 8- or 16-bit parallel port that supports interfaces to off-chip
• DMA controller
• Six full-duplex serial ports (four on the ADSP-21261)
• SPI-compatible interface
• Digital audio interface that includes two precision clock
plier, shifter, and data register file
transfers between memory and the core at every core pro­
cessor cycle
tion, PWM capture/pulse width measurement, and
external event counter capabilities
(up to 4M bit)
memory peripherals
generators (PCG), an input data port (IDP), six serial ports,
eight serial interfaces, a 20-bit synchronous parallel input
port, 10 interrupts, six flag outputs, six flag inputs, three
programmable timers, and a flexible signal routing unit
(SRU)
shows one sample configuration of a SPORT using the
on Page 1
2
S ADC and an
illustrates the