saa7803 NXP Semiconductors, saa7803 Datasheet - Page 42

• Manufacturer Part Number: saa7803
• Description: Saa7803 One Chip Cd Audio Device
• Manufacturer: NXP Semiconductors

Philips Semiconductors
9397 750 13695
Objective data sheet
6.6.7.10 EBU interface
Compliant with the I
are all clocked on the falling edge of the I
The I
can be gated off by the channel decoder. In slave mode, the bclk is continuously running.
To prevent the internal FIFO from overflow, the filling of the buffer must be regulated (see
Section “Data latency and FIFO operation” on page
Bclk and WCLK can either be input (generated outside the channel decoder) or output
(generated internally in the clock control block). Selection can be done via bits WCLKSEL
and BCLKSEL in register IISConfig.
The I
register BitClockConfig. The I
In case of gated bit clock, when BitClockConfig(BCLKGEN) is ‘1’, the speed must be
configured such that the maximum rate available on the bus is 20 % higher than the
average data throughput rate. Or in other words: the bus should have at least 20 % idle
time in between 2 bursts of data.
Default after reset, the I
activated via register IISConfig. This register also contains the possibility to kill the I
interface, such that all data line outputs go LOW.
The channel decoder contains a digital one wire EBU or SPDIF output interface. It formats
data according to the IEC60958 specification. The EBU rate can be selected to be 1
2
For proper operation of the EBU interface, the I
generated, bit clock gating must be disabled and the following relationship between
EBUClk, bclk, WCLK and I
EBUClk = WCLK
Some fields in the user channel of the EBU-stream can be filled in by software, configured
via register EBUConfig.
Bit IISConfig(KILLEBU) contains the possibility to ’kill’ the EBU interface, so that the line
outputs go LOW.
•
•
•
•
•
CD, by programming register EBUClockConfig.
Bclk: all other I
WCLK: indicates the start of a new 16/18-bit word on the data line, and differentiates
between left and right sample
DATA: 16/18-bit data words are outputted via this line, 1-bit / bclk-period
Error Flag (EF): contains the byte reliability flag; bytes that are indicated as erasures
(possible errors) after C1 and C2 correction, are flagged.
SYNC: indicates that the serial subcode line contains the MSB of a subcode word; it
will be asserted every six WCLK periods for half a WCLK period. If a subcode sync is
transferred on the subcode line, this signal will be asserted for a full WCLK period.
2
2
S-bus interface can either work in master or slave mode. In master mode, the bclk
S-bus output rate is determined by the speed of the bclk, which is configured via
2
64
2
S-bus signals are clocked on bclk
S-bus specification, the I
Rev. 01 — 19 April 2005
2
S-bus pins on the IC will be put into 3-state. They can be
2
S-bus format must be true:
2
S-bus interface can be configured to run at 1
2
S-bus bit clock signal bclk:
2
S-bus signals WCLK, DATA, EF and SYNC
2
S-bus bit clock must be internally
35).
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
One chip CD audio device
SAA7803
or 2
2
42 of 74
S-bus
CD.
or