mc68hc908gr8b Freescale Semiconductor, Inc, mc68hc908gr8b Datasheet - Page 126
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mc68hc908gr8b
Manufacturer Part Number
mc68hc908gr8b
Description
M68hc08 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.MC68HC908GR8B.pdf
(260 pages)
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Input/Output (I/O) Ports
RxD — SCI Receive Data Input
TxD — SCI Transmit Data Output
12.6.2 Data Direction Register E
Data direction register E (DDRE) determines whether each port E pin is an input or an output. Writing a 1
to a DDRE bit enables the output buffer for the corresponding port E pin; a 0 disables the output buffer.
DDRE1–DDRE0 — Data Direction Register E Bits
Figure 12-19
126
The PTE1/RxD pin is the receive data input for the ESCI module. When the enable SCI bit, ENSCI, is
clear, the ESCI module is disabled, and the PTE1/RxD pin is available for general-purpose I/O. See
Chapter 13 Serial Communications Interface (SCI)
The PTE0/TxD pin is the transmit data output for the ESCI module. When the enable SCI bit, ENSCI,
is clear, the ESCI module is disabled, and the PTE0/TxD pin is available for general-purpose I/O. See
Chapter 13 Serial Communications Interface (SCI)
These read/write bits control port E data direction. Reset clears DDRE1–DDRE0, configuring all port
E pins as inputs.
1 = Corresponding port E pin configured as output
0 = Corresponding port E pin configured as input
shows the port E I/O logic.
Address:
Avoid glitches on port E pins by writing to the port E data register before
changing data direction register E bits from 0 to 1.
Reset:
Read:
Write:
READ DDRE ($000C)
WRITE DDRE ($000C)
WRITE PTE ($0008)
READ PTE ($0008)
$000C
Bit 7
0
0
Figure 12-18. Data Direction Register E (DDRE)
= Unimplemented
6
0
0
RESET
MC68HC908GR8B Data Sheet, Rev. 3.0
Figure 12-19. Port E I/O Circuit
5
0
0
NOTE
DDREx
PTEx
4
0
0
Module.
Module.
3
0
0
2
0
0
DDRE1
1
0
Freescale Semiconductor
DDRE0
Bit 0
PTEx
0
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