mc68hc908gr8b Freescale Semiconductor, Inc, mc68hc908gr8b Datasheet - Page 74

• Manufacturer Part Number: mc68hc908gr8b
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Configuration Register (CONFIG)
OSCSTOPENB — Oscillator Stop Mode Enable Bar Bit
SCIBDSRC — SCI Baud Rate Clock Source Bit
COPRS — COP Rate Select Bit
LVISTOP — LVI Enable in Stop Mode Bit
LVIRSTD — LVI Reset Disable Bit
LVIPWRD — LVI Power Disable Bit
74
OSCSTOPENB, when set, will enable the oscillator to continue to generate clocks in stop mode. See
Chapter 4 Clock Generator Module
the rest of the MCU stops. See
cease to generate clocks while in stop mode. The default state for this option is clear, disabling the
oscillator in stop mode.
SCIBDSRC controls the clock source used for the serial communications interface (SCI). The setting
of this bit affects the frequency at which the SCI operates.See
Interface (SCI)
COPRS selects the COP timeout period. Reset clears COPRS. See
Properly (COP) Module
Setting the LVISTOP bit enables the LVI to operate during stop mode. Reset clears LVISTOP.
LVIRSTD disables the reset signal from the LVI module. See
LVIPWRD disables the LVI module. See
1 = Oscillator enabled to operate during stop mode
0 = Oscillator disabled during stop mode (default)
1 = Internal bus clock used as clock source for SCI
0 = External oscillator used as clock source for SCI
1 = COP timeout period = 8176 CGMXCLK cycles
0 = COP timeout period = 262,128 CGMXCLK cycles
1 = LVI enabled during stop mode
0 = LVI disabled during stop mode
0 = LVI module resets enabled
0 = LVI module power enabled
Note: LVI5OR3 bit is only reset via POR (power-on reset).
Address:
Reset:
Read:
Write:
Module.
COPRS
$001F
Bit 7
0
On the MC68HC908GR8B, LVIPWRD is always clear.
On the MC68HC908GR8B, LVIRSTD is always clear.
Figure 5-2. Configuration Register 1 (CONFIG1)
LVISTOP
6
0
Chapter 16 Timebase Module
MC68HC908GR8B Data Sheet, Rev. 3.0
LVIRSTD
(CGM). This function is used to keep the timebase running while
5
0
Chapter 11 Low-Voltage Inhibit
LVIPWRD
NOTE
NOTE
4
0
LVI5OR3
See note
3
Chapter 11 Low-Voltage Inhibit
(TBM). When clear, the oscillator will
Chapter 13 Serial Communications
SSREC
2
0
Chapter 6 Computer Operating
(LVI).
STOP
1
0
Freescale Semiconductor
COPD
Bit 0
0
(LVI).