mc68hc908gr8b Freescale Semiconductor, Inc, mc68hc908gr8b Datasheet - Page 56

• Manufacturer Part Number: mc68hc908gr8b
• Description: M68hc08 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Clock Generator Module (CGM)
frequency, f
comparison.
4.3.4 Acquisition and Tracking Modes
The PLL filter is manually or automatically configurable into one of two operating modes:
4.3.5 Manual and Automatic PLL Bandwidth Modes
The PLL can change the bandwidth or operational mode of the loop filter manually or automatically.
Automatic mode is recommended for most users.
In automatic bandwidth control mode (AUTO = 1), the lock detector automatically switches between
acquisition and tracking modes. Automatic bandwidth control mode also is used to determine when the
VCO clock, CGMVCLK, is safe to use as the source for the base clock, CGMOUT. (See
Bandwidth Control
request and then check the LOCK bit. If interrupts are disabled, software can poll the LOCK bit
continuously (during PLL startup, usually) or at periodic intervals. In either case, when the LOCK bit is set,
the VCO clock is safe to use as the source for the base clock. (See
the VCO is selected as the source for the base clock and the LOCK bit is clear, the PLL has suffered a
severe noise hit and the software must take appropriate action, depending on the application. (See
Interrupts
The following conditions apply when the PLL is in automatic bandwidth control mode:
The PLL also may operate in manual mode (AUTO = 0). Manual mode is used by systems that do not
require an indicator of the lock condition for proper operation. Such systems typically operate well below
f
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BUSMAX
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Acquisition mode — In acquisition mode, the filter can make large frequency corrections to the
VCO. This mode is used at PLL startup or when the PLL has suffered a severe noise hit and the
VCO frequency is far off the desired frequency. When in acquisition mode, the ACQ bit is clear in
the PLL bandwidth control register. (See
Tracking mode — In tracking mode, the filter makes only small corrections to the frequency of the
VCO. PLL jitter is much lower in tracking mode, but the response to noise is also slower. The PLL
enters tracking mode when the VCO frequency is nearly correct, such as when the PLL is selected
as the base clock source. (See
tracking mode when not in acquisition mode or when the ACQ bit is set.
The ACQ bit (see
filter. (See
The ACQ bit is set when the VCO frequency is within a certain tolerance and is cleared when the
VCO frequency is out of a certain tolerance. (See
more information.)
The LOCK bit is a read-only indicator of the locked state of the PLL.
The LOCK bit is set when the VCO frequency is within a certain tolerance and is cleared when the
VCO frequency is out of a certain tolerance. (See
more information.)
CPU interrupts can occur if enabled (PLLIE = 1) when the PLL’s lock condition changes, toggling
the LOCK bit. (See
.
for information and precautions on using interrupts.)
RCLK
. The circuit determines the mode of the PLL and the lock condition based on this
4.3.4 Acquisition and Tracking
Register.) If PLL interrupts are enabled, the software can wait for a PLL interrupt
4.5.2 PLL Bandwidth Control
4.5.1 PLL Control
MC68HC908GR8B Data Sheet, Rev. 3.0
4.3.8 Base Clock Selector
Register.)
4.5.2 PLL Bandwidth Control
Modes.)
Register) is a read-only indicator of the mode of the
4.8 Acquisition/Lock Time Specifications
4.8 Acquisition/Lock Time Specifications
Circuit.) The PLL is automatically in
4.3.8 Base Clock Selector
Register.)
Freescale Semiconductor
4.5.2 PLL
Circuit.) If
for
for
4.6