mc68hc908gr8b Freescale Semiconductor, Inc, mc68hc908gr8b Datasheet - Page 94

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mc68hc908gr8b

Manufacturer Part Number
mc68hc908gr8b
Description
M68hc08 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet
External Interrupt (IRQ)
When an interrupt pin is both falling-edge and low-level triggered (MODE = 1), the interrupt remains set
until both of these events occur:
The vector fetch or software clear may occur before or after the interrupt pin returns to a high level. As
long as the pin is low, the interrupt request remains pending. A reset will clear the latch and the MODE
control bit, thereby clearing the interrupt even if the pin stays low.
When set, the IMASK bit in the INTSCR masks all external interrupt requests. A latched interrupt request
is not presented to the interrupt priority logic unless the IMASK bit is clear.
94
$001D
Addr.
Vector fetch or software clear
Return of the interrupt pin to a high level
IRQ
IRQ Status and Control
Register Name
Register (INTSCR)
The interrupt mask (I) in the condition code register (CCR) masks all
interrupt requests, including external interrupt requests.
DECODER
V
VECTOR
FETCH
DD
RESET
See page 96.
ACK
INTERNAL
PULLUP
DEVICE
Reset:
Read:
Write:
Figure 8-1. IRQ Module Block Diagram
Figure 8-2. IRQ I/O Register Summary
V
MODE
DD
MC68HC908GR8B Data Sheet, Rev. 3.0
Bit 7
0
0
D
CK
CLR
= Unimplemented
Q
6
0
0
NOTE
5
0
0
IMASK
SYNCHRONIZER
4
0
0
VOLTAGE
DETECT
HIGH
IRQF
3
0
ACK
2
0
0
IRQF
Freescale Semiconductor
IMASK
1
0
TO CPU FOR
BIL/BIH
INSTRUCTIONS
IRQ
INTERRUPT
REQUEST
TO MODE
SELECT
LOGIC
MODE
Bit 0
0

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