mc68hc908as60 Freescale Semiconductor, Inc, mc68hc908as60 Datasheet - Page 177

• Manufacturer Part Number: mc68hc908as60
• Description: Mc68hc908as60 Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

10.10.2 Parametric Influences on Reaction Time
MC68HC908AS60 — Rev. 1.0
a certain tolerance of the desired frequency regardless of the size of the
initial error.
The discrepancy in these definitions makes it difficult to specify an
acquisition or lock time for a typical PLL. Therefore, the definitions for
acquisition and lock times for this module are:
Obviously, the acquisition and lock times can vary according to how
large the frequency error is and may be shorter or longer in many cases.
Acquisition and lock times are designed to be as short as possible while
still providing the highest possible stability. These reaction times are not
constant, however. Many factors directly and indirectly affect the
acquisition time.
The most critical parameter which affects the reaction times of the PLL
is the reference frequency, f
detector and controls how often the PLL makes corrections. For stability,
the corrections must be small compared to the desired frequency, so
several corrections are required to reduce the frequency error.
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Acquisition time, t
between the actual output frequency and the desired output
frequency to less than the tracking mode entry tolerance,
Acquisition time is based on an initial frequency error,
(f
bandwidth control mode (see
PLL Bandwidth
bit becomes set in the PLL bandwidth control register (PBWC).
Lock time, t
between the actual output frequency and the desired output
frequency to less than the lock mode entry tolerance,
time is based on an initial frequency error, (f
not more than 100 percent. In automatic bandwidth control
mode, lock time expires when the LOCK bit becomes set in the
PLL bandwidth control register (PBWC). See
and Automatic PLL Bandwidth
DES
Clock Generator Module (CGM)
– f
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ORIG
Lock
)/f
DES
, is the time the PLL takes to reduce the error
Modes), acquisition time expires when the ACQ
ACQ
, of not more than 100 percent. In automatic
, is the time the PLL takes to reduce the error
RDV
. This frequency is the input to the phase
10.4.2.3 Manual and Automatic
Modes.
Acquisition/Lock Time Specifications
Clock Generator Module (CGM)
DES
10.4.2.3 Manual
– f
ORIG
Technical Data
Lock
)/f
DES
. Lock
trk
.
, of