mc68hc908as60 Freescale Semiconductor, Inc, mc68hc908as60 Datasheet - Page 243

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mc68hc908as60

Manufacturer Part Number
mc68hc908as60
Description
Mc68hc908as60 Microcontroller
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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MC68HC908AS60 — Rev. 1.0
NOTE:
Address:
LOOPS — Loop Mode Select Bit
ENSCI — Enable SCI Bit
TXINV — Transmit Inversion Bit
Setting the TXINV bit inverts all transmitted values, including idle, break,
start, and stop bits.
M — Mode (Character Length) Bit
Reset:
Read:
Write:
This read/write bit enables loop mode operation. In loop mode the
RxD pin is disconnected from the SCI, and the transmitter output goes
into the receiver input. Both the transmitter and the receiver must be
enabled to use loop mode. Reset clears the LOOPS bit.
This read/write bit enables the SCI and the SCI baud rate generator.
Clearing ENSCI sets the SCTE and TC bits in SCI status register 1
and disables transmitter interrupts. Reset clears the ENSCI bit.
This read/write bit reverses the polarity of transmitted data. Reset
clears the TXINV bit.
This read/write bit determines whether SCI characters are eight or
nine bits long. (See
stop bit, as a receiver wakeup signal, or as a parity bit. Reset clears
the M bit.
Freescale Semiconductor, Inc.
For More Information On This Product,
1 = Loop mode enabled
0 = Normal operation enabled
1 = SCI enabled
0 = SCI disabled
1 = Transmitter output inverted
0 = Transmitter output not inverted
1 = 9-bit SCI characters
0 = 8-bit SCI characters
LOOPS
Serial Communications Interface (SCI)
$0013
Bit 7
0
Figure 17-9. SCI Control Register 1 (SCC1)
Go to: www.freescale.com
ENSCI
6
0
Table
TXINV
5
0
17-5.) The ninth bit can serve as an extra
M
4
0
Serial Communications Interface (SCI)
WAKE
3
0
ILTY
2
0
PEN
1
0
Technical Data
I/O Registers
Bit 0
PTY
0

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