mc68hc908as60 Freescale Semiconductor, Inc, mc68hc908as60 Datasheet - Page 275

• Manufacturer Part Number: mc68hc908as60
• Description: Mc68hc908as60 Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

MC68HC908AS60 — Rev. 1.0
The SPI transmitter interrupt enable bit (SPTIE) enables the SPTE flag
to generate transmitter CPU interrupt requests.
The SPI receiver interrupt enable bit (SPRIE) enables the SPRF bit to
generate receiver CPU interrupt, provided that the SPI is enabled
(SPE = 1).
The error interrupt enable bit (ERRIE) enables both the MODF and
OVRF flags to generate a receiver/error CPU interrupt request.
The mode fault enable bit (MODFEN) can prevent the MODF flag from
being set so that only the OVRF flag is enabled to generate
receiver/error CPU interrupt requests.
Two sources in the SPI status and control register can generate CPU
interrupt requests:
1. SPI receiver full bit (SPRF) — The SPRF bit becomes set every
2. SPI transmitter empty (SPTE) — The SPTE bit becomes set every
ERRIE
MODF
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OVRF
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time a byte transfers from the shift register to the receive data
register. If the SPI receiver interrupt enable bit, SPRIE, is also set,
SPRF can generate an SPI receiver/error CPU interrupt request.
time a byte transfers from the transmit data register to the shift
register. If the SPI transmit interrupt enable bit, SPTIE, is also set,
SPTE can generate an SPTE CPU interrupt request.
Serial Peripheral Interface (SPI)
Figure 18-9. SPI Interrupt Request Generation
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SPRIE
SPTE
SPTIE
SPRF
SPE
Serial Peripheral Interface (SPI)
SPI TRANSMITTER
CPU INTERRUPT REQUEST
SPI RECEIVER/ERROR
CPU INTERRUPT REQUEST
Technical Data
Interrupts