mc68hc912dg128 Freescale Semiconductor, Inc, mc68hc912dg128 Datasheet - Page 102

• Manufacturer Part Number: mc68hc912dg128
• Description: M68hc12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Bus Control and Input/Output
Technical Data
102
CGMTE — Clock Generator Module Testing Enable
PIPOE — Pipe Status Signal Output Enable
NECLK — No External E Clock
Freescale Semiconductor, Inc.
NDBE controls the use of the DBE pin of Port E. The NDBE bit has no
effect in Single Chip or Peripheral Modes. The associated pin will
default to the CAL function if the CALE bit is set in PEAR register or
otherwise to an I/O.
Normal: write never; Special: write anytime EXCEPT the first. Read
anytime.
Normal: write once; Special: write anytime EXCEPT the first time.
Read anytime.
Normal single chip: write once; special single chip: write anytime; all
other modes: write never.
Read anytime. In peripheral mode, E is an input and in all other
modes, E is an output.
For More Information On This Product,
0 = PE6 is general-purpose I/O or pipe output.
1 = PE6 is a test signal output from the CGM module (no effect in
0 = PE[6:5] are general-purpose I/O (if CGMTE = 1, PE6 is a test
1 = PE[6:5] are outputs and indicate the state of the instruction
0 = PE4 is the external E-clock pin subject to the following
1 = PE4 is a general-purpose I/O pin.
single chip or normal expanded modes). PIPOE = 1 overrides
this function and forces PE6 to be a pipe status output signal.
output signal from the CGM module).
queue (only effective in expanded modes).
limitation: In single-chip modes, to get an E clock output signal,
it is necessary to have ESTR = 0 in addition to NECLK = 0. A
16-bit write to PEAR and MODE registers can configure all
three bits in one operation.
Bus Control and Input/Output
Go to: www.freescale.com
MC68HC912DG128 — Rev 3.0
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