mc68hc912dg128 Freescale Semiconductor, Inc, mc68hc912dg128 Datasheet - Page 166
mc68hc912dg128
Manufacturer Part Number
mc68hc912dg128
Description
M68hc12 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.MC68HC912DG128.pdf
(452 pages)
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Clock Functions
11.6.3 STOP Exit and Fast STOP Recovery
Technical Data
166
NOTE:
Stop mode is entered when a STOP instruction is executed. Recovery
from STOP depends primarily on the state of the three status bits
NOLHM, CME & DLY.
The DLY bit controls the duration of the waiting period between the
actual exit for some key blocks (e.g. clock monitor, clock generators) and
the effective exit from stop for all the rest of the MCU. DLY=1 enables
the 13-stage counter to generate a 4096 count delay. DLY=0 selects no
delay. As the XCLK is derived from the slow mode divider, the value in
the SLOW register modifies the actual delay time.
DLY=0 is only recommended when there is a good signal available
at the EXTAL pin (e.g. an external square wave source).
STOP mode is exited with an external reset, an external interrupt from
IRQ or XIRQ, a Key Wake-Up interrupt from port J or port H, or an
MSCAN Wake-Up interrupt.
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
Clock Functions
MC68HC912DG128 — Rev 3.0
MOTOROLA
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