mc68hc912dg128 Freescale Semiconductor, Inc, mc68hc912dg128 Datasheet - Page 277

• Manufacturer Part Number: mc68hc912dg128
• Description: M68hc12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

15.5.1 START Signal
15.5.2 Slave Address Transmission
15.5.3 Data Transfer
MC68HC912DG128 — Rev 3.0
MOTOROLA
NOTE:
When the bus is free, i.e. no master device is engaging the bus (both
SCL and SDA lines are at logical high), a master may initiate
communication by sending a START signal. As shown in
START signal is defined as a high-to-low transition of SDA while SCL is
high. This signal denotes the beginning of a new data transfer (each data
transfer may contain several bytes of data) and wakes up all slaves.
The first byte of data transfer immediately after the START signal is the
slave address transmitted by the master. This is a seven-bit calling
address followed by a R/W bit. The R/W bit tells the slave the desired
direction of data transfer.
Only the slave with a calling address that matches the one transmitted
by the master will respond by sending back an acknowledge bit. This is
done by pulling the SDA low at the 9th clock (see
Once successful slave addressing is achieved, the data transfer can
proceed byte-by-byte in a direction specified by the R/W bit sent by the
calling master.
All transfers that come after an address cycle are referred to as data
transfers, even if they carry sub-address information for the slave
device.
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1 = Read transfer, the slave transmits data to the master.
0 = Write transfer, the master transmits data to the slave.
Slave address - No two slaves in the system may have the same
address. If the IIC is master, it must not transmit an address that
is equal to its own slave address. The IIC cannot be master and
slave at the same time. If however arbitration is lost during an
address cycle the IIC will revert to slave mode and operate
correctly even if it is being addressed by another master.
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Inter-IC Bus
Figure
Figure
15-2).
Technical Data
Inter-IC Bus
IIC Protocol
15-2, a
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