spc560p50l3 STMicroelectronics, spc560p50l3 Datasheet - Page 13

• Manufacturer Part Number: spc560p50l3
• Description: 32-bit Power Architecture? Based Mcu For Chassis & Safety Applications
• Manufacturer: STMicroelectronics

SPC560P44Lx, SPC560P50Lx
3.2.5
3.2.6
The flash memory module provides the following features:
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On-chip SRAM with ECC
The SPC560Px SRAM module provides a general-purpose memory of as much as 40 KB.
ECC handling is done on a 32-bit boundary and is completely software compatible with
MPC55xx family devices with an e200z6 core and 64-bit wide ECC.
The SRAM module provides the following features:
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Interrupt Controller (INTC)
The INTC (Interrupt Controller) provides priority-based preemptive scheduling of interrupt
requests, suitable for statically scheduled hard real-time systems.
For high priority interrupt requests, the time from the assertion of the interrupt request from
the peripheral to when the processor is executing the Interrupt Service Routine (ISR) has
been minimized. The INTC provides a unique vector for each interrupt request source for
quick determination of which ISR needs to be executed. It also provides an ample number of
As much as 576 KB flash memory
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Four 128-bit wide prefetch buffers to provide single cycle in-line accesses (prefetch
buffers can be configured to prefetch code or data or both)
Typical flash memory access time: 0 wait-states for buffer hits, 3 wait-states for page
buffer miss at 60 MHz
Hardware managed flash memory writes handled by 32-bit RISC Krypton engine
Hardware and software configurable read and write access protections on a per-master
basis.
Configurable access timing allowing use in a wide range of system frequencies.
Multiple-mapping support and mapping-based block access timing (0–31 additional
cycles) allowing use for emulation of other memory types.
Software programmable block program/erase restriction control.
Erase of selected block(s)
Read page size of 128 bits (4 words)
64-bit ECC with single-bit correction, double-bit detection for data integrity
Embedded hardware program and erase algorithm
Erase suspend, program suspend and erase-suspended program
Censorship protection scheme to prevent flash memory content visibility
Hardware support for EEPROM emulation
Supports read/write accesses mapped to the SRAM memory from any master
40 KB general purpose RAM
Supports byte (8-bit), half word (16-bit), and word (32-bit) writes for optimal use of
memory
Typical SRAM access time: 0 wait-state for reads and 32-bit writes; 1 wait state for 8-
and 16-bit writes if back to back with a read to same memory block
8 blocks (32 KB + 2×16 KB + 32 KB + 32 KB + 3×128 KB) code flash
4 blocks (16 KB + 16 KB + 16 KB + 16 KB) data flash
Full Read While Write (RWW) capability between code and data flash
Doc ID 13950 Rev 5
Overview of the SPC560Px
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