spc560p50l3 STMicroelectronics, spc560p50l3 Datasheet - Page 22

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spc560p50l3

Manufacturer Part Number
spc560p50l3
Description
32-bit Power Architecture? Based Mcu For Chassis & Safety Applications
Manufacturer
STMicroelectronics
Datasheet

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Overview of the SPC560Px
3.2.24
3.2.25
22/31
eTimer
Six 16-bit general purpose up/down timer/counter units per module are implemented with
the following features:
Analog-to-Digital Converter (ADC) module
The ADC module provides the following features:
Analog part:
Individual channel capability
Maximum count rate
Counters are cascadable
Programmable count modulo
Quadrature decode capabilities
Counters can share available input pins
Count once or repeatedly
Counters are pre-loadable
Pins available as GPIO when timer functionality not in use
Two on-chip AD converters
Input capture trigger
Output compare
Double buffer (to capture rising edge and falling edge)
Separate prescaler for each counter
Selectable clock source
0 % - 100 % pulse measurement
Rotation direction flag (Quad decoder mode)
10-bit AD resolution
One sample and hold unit per ADC
Conversion time, including sampling time, less than 1 μs (at full precision)
Typical sampling time is 150 ns min. (at full precision)
Differential Non-Linearity error (DNL) ±1 LSB
Integral Non-Linearity error (INL) ±1.5 LSB
TUE <3 LSB
Single-ended input signal range from 0 to 3.3 V
The ADC and its reference can be supplied with a voltage independent from V
The ADC supply can be equal or higher than V
The ADC supply and the ADC reference are not independent from each other
(they are internally bonded to the same pad)
Sample times of 2 (default), 8, 64, or 128 ADC clock cycles
Doc ID 13950 Rev 5
DDIO
SPC560P44Lx, SPC560P50Lx
DDIO

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