spc560p50l3 STMicroelectronics, spc560p50l3 Datasheet - Page 25
spc560p50l3
Manufacturer Part Number
spc560p50l3
Description
32-bit Power Architecture? Based Mcu For Chassis & Safety Applications
Manufacturer
STMicroelectronics
Datasheet
1.SPC560P50L3.pdf
(31 pages)
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SPC560P44Lx, SPC560P50Lx
3.2.30
The JTAG controller provides the following features:
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On-chip Voltage Regulator (VREG)
The on-chip voltage regulator module provides the following features:
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IEEE Test Access Port (TAP) interface 4 pins (TDI, TMS, TCK, TDO)
Selectable modes of operation include JTAGC/debug or normal system operation.
5-bit instruction register that supports the following IEEE 1149.1-2001 defined
instructions:
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5-bit instruction register that supports the additional following public instructions:
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Three test data registers:
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TAP controller state machine that controls the operation of the data registers,
instruction register and associated circuitry.
Uses external NPN transistor
Regulates external 3.3 V down to 1.2 V for the core logic
Low voltage detection on the internal 1.2 V and I/O voltage 3.3 V
BYPASS, IDCODE, EXTEST, SAMPLE, SAMPLE/PRELOAD
ACCESS_AUX_TAP_NPC, ACCESS_AUX_TAP_ONCE
Bypass register
Boundary scan register
Device identification register
Doc ID 13950 Rev 5
Overview of the SPC560Px
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