gc80c510 CORERIVER Semiconductor, gc80c510 Datasheet - Page 19

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gc80c510

Manufacturer Part Number
gc80c510
Description
Eprom/rom 8-bit Turbo Microcontrollers
Manufacturer
CORERIVER Semiconductor
Datasheet
6 Functional Description
6.1 CPU Description
6.1.1 Memory Organization
6.1.1.1 Program Memory
MiDAS1.1 Family
of program and data memory allows the data memory to be accessed by 8-bit addresses, which can be
quickly stored and manipulated by an 8-bit CPU.
Figure 6-1 Memory Organization
execution from location 0000H.
causes the CPU to jump to that location, where it commences execution of the service routine. External
Interrupt 0 (INT0B), for example, is assigned to location 0003h. If External Interrupt 0 is going to be
used, its service routine must begin at location 0003h. If the interrupt is not going to be used, its service
MiDAS1.1 family has separate address spaces for program and data memory. The logical separation
Program Memory can only be read, not written to. There can be up to 4K bytes of Program Memory.
The left part of
As shown in
000h
3FFh
Interrupt Vector
Figure
(4kBytes)
Figure 6-1
Internal
ROM
6-1, each interrupt is assigned a fixed location in Program Memory. The interrupt
shows a map of the Program Memory. After reset, the CPU begins
30H
20H
00H
R0
R0
R0
R0
R0
R0
R0
R0
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R1
R1
R1
R1
16x8bit (128bit)
R1
R1
R1
R1
16x8bit (128bit)
Bit Addressable
Bit Addressable
(Scratch Pad)
(Scratch Pad)
R2
R2
R2
R2
R2
R2
R2
R2
80 x 8bit
80 x 8bit
R3
R3
R3
R3
R3
R3
R3
R3
R4
R4
R4
R4
R4
R4
R4
R4
R5
R5
R5
R5
R5
R5
R5
R5
R6
R6
R6
R6
R6
R6
R6
R6
R7
R7
R7
R7
R7
R7
R7
R7
BANK 3
BANK 2
BANK 1
BANK 0
7FH
2FH
80h
00h
(Indirect or
Internal
Direct)
RAM
FFh
Direct)
(Only
SFR

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