gc80c510 CORERIVER Semiconductor, gc80c510 Datasheet - Page 202

• Manufacturer Part Number: gc80c510
• Description: Eprom/rom 8-bit Turbo Microcontrollers
• Manufacturer: CORERIVER Semiconductor

13.27 PWMCON (DCh) : PWM Control Register
Symbol
PS2_P0
PS1_P0
PS0_P0
Bit No.
P0SEL
RWT
EWT
Enable Watchdog Timer Reset.
Restart Watchdog Timer.
PWM Waveform Output Enable to P0[6].
Prescaled Clock Selection.
R/W(0)
PS2_P0
P0SEL
has no effect on the ability of the watchdog timer to generate a watchdog interrupt.
The time-out period of the watchdog timer is controlled by the Watchdog Timer Mode
Select bits (CKCON.7-6). Clearing these bits will disable the ability of the watchdog
timer to generate a reset, but have no affect on the timer itself, or its ability to
generate a watchdog timer interrupt.
0 = A time-out of the watchdog timer will not cause the device to reset.
1 = A time-out of the watchdog timer will cause the device to reset.
software must set the RWT bit if the Watchdog is enabled. Failing to set the RWT will
cause a reset when the time-out has elapsed. There is no need to set the RWT bit to a
0 because it is self-clearing.
is restarted, WDT mode can be changed to mode 3 or any mode.
0 = Disable the PWM waveform output to P[6].
1 = Enable the PWM waveform output to P[6].
Note that PWM clock (F
This bit enables/disables the ability of the watchdog timer to reset the device. This bit
This bit serves as the strobe for the Watchdog function. During the time-out period,
Note that RWT flag bit must be set to “1” at only WDT mode 0.
7
0
0
0
0
PS2_P0
R/W(0)
PS1_P0
6
0
0
1
1
PS1_P0
R/W(0)
PWM
PS0_P0
5
Page 202 of 211
) to ADC should not be set to F
0
1
0
1
PS0_P0
R/W(0)
4
Description
3
(Default)
-
PWM Clock Rate (F
R/W(0)
PWMF
Appendix B: SFR description
F
F
F
F
OSC
OSC
OSC
OSC
OSC
2
/1.
/ 1
/ 2
/ 4
/ 8
After watchdog timer
CLR_P0
R/W(0)
PWM
1
)
RUN_P0
R/W(0)
0