gc80c510 CORERIVER Semiconductor, gc80c510 Datasheet - Page 81

• Manufacturer Part Number: gc80c510
• Description: Eprom/rom 8-bit Turbo Microcontrollers
• Manufacturer: CORERIVER Semiconductor

MiDAS1.1 Family
interrupts are polled and their priority is resolved. If certain conditions are met then the hardware will
execute an internally generated LCALL instruction which will vector the process to the appropriate
interrupt vector address. The conditions for generating the LCALL are
repeated every machine cycle, with the interrupts sampled in the same machine cycle. Then note that if
an interrupt flag is active but not being responded to for one of the above conditions, and is not still
active when the blocking condition is removed, the denied interrupt will not be serviced. This means
that active interrupts are not remembered; every polling cycle is new.
Timer/Counter 0
Timer/Counter 1
Figure 6-19 Hierarchy of Interrupt Priority
The interrupt flags are sampled every machine cycle. In the same machine cycle, the sampled
If any of these conditions are not met, then the LCALL will not be generated. The polling cycle is
1.
2.
3.
UART
PWM
INT0
INT1
INT2
INT3
WDT
ADC
An interrupt of equal or higher priority is not currently being services.
The current polling cycle is the last machine cycle of the instruction currently being executed.
The current instruction does not involve a write to IP, IE, EIP, EIE, IPH or EXIF and is not a
RETI.
IT0
IT1
1
0
1
0
RI
TI
Flag Bits
PWMF
ADCF
WDIF
TF0
TF1
IE0
IE1
IE2
IE3
Interrupt Enable Bits
EPWM
EWDT
EADC
EX2
EX3
EX0
ET0
EX1
ET1
ES
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EA
PPWM
PWDT
PADC
PX0
PT0
PX1
PT1
PX2
PX3
PS
Priority
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
High Priority
Low Priority
High Priority
High Priority
Interrupt
Low Priority
Interrupt
Interrupt
Vector