gc80c510 CORERIVER Semiconductor, gc80c510 Datasheet - Page 79

• Manufacturer Part Number: gc80c510
• Description: Eprom/rom 8-bit Turbo Microcontrollers
• Manufacturer: CORERIVER Semiconductor

6.2.8 Interrupt
6.2.8.1 Interrupt Sources
MiDAS1.1 Family
interrupt sources has an individual priority bit, flag, interrupt vector and enable bit. In addition, the
interrupts can be globally enabled or disabled.
depending on bits IT0 and IT1 of the TCON register. The bits IE0 and IE1 in the TCON register are the
flags which are checked to generate the interrupt. Another two external interrupts of INT2 and INT3B
are only edge triggered type. INT2 is positive edge triggered type but INT3B is negative edge triggered
type. In the negative edge triggered mode, the external interrupts are sampled in every machine cycle.
If the sample is high in one cycle and low in the next, then a high to low transition is detected and the
interrupts request flag IE0 or IE1 in TCON or IE3 in EXIF[5] is set. In the positive edge triggered mode,
a low-to-high transition is detected. The flag bit requests the interrupt. Since the external interrupts are
sampled every machine cycle, they have to be held high or low for at least one complete machine cycle.
If IEx in TCON is selected to level triggered mode (ITx=0), then the requesting source has to hold the
pin low till the interrupt is serviced. The IE0 and IE1 will not be cleared by the hardware on entering the
service routine in this mode. If the interrupt continues to be held low even after the service routine is
completed, then the processor may acknowledge another interrupt request from the same source.
the service routine is called. But, note that the external interrupts INT2 and INT3B are edge triggered
only. The individual interrupt flag corresponding to external interrupt 2 and 3 must be cleared manually
by software.
overflow in the Timer 0 and 1. The TF0 and TF1 flags are automatically cleared by the hardware when
the timer interrupt is serviced.
time-out count is reached, the Watchdog timer interrupt flag WDIF (WDCON.3) is set. If the interrupt is
enabled by the enable bit EIE.4, then an interrupt occurs.
the UART, which are obtained by the RI and TI bits in the SCON. These bits are not automatically
cleared by the hardware, and the user must clear these bits using software.
signal goes “0” to “1” if PWM interrupt enable bit (EIE.5) is “1’. This PWMF are not automatically cleared
by the hardware, and the user must clear these bits using software.
The MiDAS1.1 family has a two priority level interrupt structure with 10 interrupt sources. Each of the
The two external interrupts INT0B and INT1B can be either edge triggered or level triggered,
If IEx in TCON is selected to edge triggered mode (ITx=1), the IEx bit is automatically cleared when
The Timer 0 and 1 interrupts are generated by the TF0 and TF1 flags. These flags are set by the
The Watchdog timer can be used as a system monitor or a simple timer. In either case, when the
The UART can generate interrupts on reception or transmission. There are two interrupt sources from
PWM block will generate an interrupt and the PWM interrupt flag PWMF is set whenever PWM output
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