gc80c510 CORERIVER Semiconductor, gc80c510 Datasheet - Page 80

• Manufacturer Part Number: gc80c510
• Description: Eprom/rom 8-bit Turbo Microcontrollers
• Manufacturer: CORERIVER Semiconductor

6.2.8.2 Priority Level Structure
ADC interrupt will be generated when ADC conversion is finished. ADCF flag will be set to “1” and
AD_END flag will be set to “1”. ADCF flag must be cleared by S/W in ADC interrupt routine.
interrupts can be generated. Each of the individual interrupts can be enabled or disabled by setting or
clearing a bit in the IE register. The IE register also has a global enable/disable bit EA which can be
cleared to disable all the interrupts.
interrupted by a lower priority interrupt. However there exists a pre-defined hierarchy amongst the
interrupts themselves. This hierarchy comes into play when the interrupt controller has to resolve
simultaneous requests having the same priority level. This hierarchy is defined as shown below; the
interrupts are numbered starting from the highest priority to the lowest.
Figure 6-18 Interrupt Vector Generation Flow
Table 6-11 Priority Structure of Interrupts
All the bits that generate interrupts can be set or reset by hardware, and thereby software initiated
There are two priority levels for the interrupts. Naturally, a higher priority interrupt cannot be
14 (Lowest)
1 (Highest)
Hierarchy
10
13
Interrupt
2
3
4
5
8
9
Sources
Interrupt
Flag bits
IE0
RI + TI
Sources
INT0B
INT3B
PWM
INT1
INT2
WDT
ADC
TF0
TF1
[Interrupt Vector Generation Flow]
Individual
Enable
bits
EX0
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Enable
Global
bits
EA
Vector Address
0003h
000Bh
0013h
001Bh
0023h
003Bh
0043h
004Bh
0063h
006Bh
Priority
bits
PX0
Generation
Polling &
Vector
0003h
Functional Description
Priority Level
Interrupt
Vector
0003h
2 Levels
2 Levels
2 Levels
2 Levels
2 Levels
2 Levels
2 Levels
2 Levels
2 Levels
2 Levels