tspc860 ATMEL Corporation, tspc860 Datasheet - Page 10

• Manufacturer Part Number: tspc860
• Description: Integrated Communication Processor
• Manufacturer: ATMEL Corporation

Table 1. Signal Descriptions (Continued)
10
KR/RETRY
SPKROUT
Name
IRQ2
IRQ4
IRQ3
RSV
TEA
CR
TA
BI
TSPC860 [Preliminary]
States During
States During
See Section
See Section
Hardware
Reset” on
Hardware
Reset” on
page 27
page 27
“Signal
“Signal
Reset
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Number
C2
D1
H3
E3
K1
F2
Active Pull-up
Active Pull-up
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Three-state
Three-state
Open-drain
Type
Input
Description
Transfer Acknowledge—Indicates that the slave device addressed in
the current transaction accepted data sent by the master (write) or
has driven the data bus with valid data (read). This is an output when
the PCMCIA interface or memory controller controls the transaction.
The only exception occurs when the memory controller controls the
slave access by means of the GPCM and the corresponding option
register is instructed to wait for an external assertion of TA. Every
slave device should negate TA after a transaction ends and
immediately three-state it to avoid bus contention if a new transfer is
initiated addressing other slave devices. TA requires the use of an
external pull-up resistor.
Transfer Error Acknowledge—Indicates that a bus error occurred in
the current transaction. The TSPC860 asserts TEA when the bus
monitor does not detect a bus cycle termination within a reasonable
amount of time. Asserting TEA terminates the bus cycle, thus
ignoring the state of TA. TEA requires the use of an external pull-up
resistor.
Burst Inhibit—Indicates that the slave device addressed in the
current burst transaction cannot support burst transfers. It acts as an
output when the PCMCIA interface or the memory controller takes
control of the transaction. BI requires the use of an external pull-up
resistor.
Reservation—The TSPC860 outputs this three-state signal in
conjunction with the address bus to indicate that the core initiated a
transfer as a result of a stwcx. or lwarx.
Interrupt Request 2—One of eight external inputs that can request
(by means of the internal interrupt controller) a service routine from
the core.
Kill Reservation—This input is used as a part of the memory
reservation protocol, when the TSPC860 initiated a transaction as
the result of a stwcx. instruction.
Retry—This input is used by a slave device to indicate it cannot
accept the transaction. The TSPC860 must relinquish mastership
and reinitiate the transaction after winning in the bus arbitration.
Interrupt Request 4 – One of eight external inputs that can request
(by means of the internal interrupt controller) a service routine from
the core. Note that the interrupt request signal that is sent to the
interrupt controller is the logical AND of this line (if defined as IRQ4)
and DP1/IRQ4 (if defined as IRQ4).
SPKROUT—Digital audio wave form output to be driven to the
system speaker.
Cancel Reservation—This input is used as a part of the storage
reservation protocol.
Interrupt Request 3—One of eight external inputs that can request
(by means of the internal interrupt controller) a service routine from
the core. Note that the interrupt request signal sent to the interrupt
controller is the logical AND of CR/IRQ3 (if defined as IRQ3) and
DP0/IRQ3 if defined as IRQ3.
2129B–HIREL–12/04