tspc860 ATMEL Corporation, tspc860 Datasheet - Page 49

• Manufacturer Part Number: tspc860
• Description: Integrated Communication Processor
• Manufacturer: ATMEL Corporation

Figure 25. Asynchronous External Master Memory Access Timing (GPCM Controlled – ACS = ’00’)
Figure 26. Asynchronous External Master – Control Signals Negation Time
Table 8. Interrupt Timing
Notes:
2129B–HIREL–12/04
Number
I39
I40
I41
I42
I43
1. The timings I39 and I40 describe the testing conditions under which the IRQ lines are tested when being defined as level
sensitive. The IRQ lines are synchronized internally and do not have to be asserted or negated with reference to the CLK-
OUT.
The timings I41, I42 and I43 are specified to allow the correct function of the IRQ lines detection circuitry, and has no direct
relation with the total system interrupt latency that the TSPC860 is able to support.
CSx, WE[0:3],
OE, GPLx,
BS[0:3]
TSIZ[0:1],
CLKOUT
Characteristic
IRQx Valid to CLKOUT Rising Edge (Set Up Time)
IRQx Hold Time After CLKOUT
IRQx Pulse Width Low
IRQx Pulse Width High
IRQx Edge to Edge Time
A[0:31],
R/W
CSx
AS
AS
(1)
B40
B39
B43
B22
4 × T
All Frequencies
Min
CLOCKOUT
6
2
3
3
Max
–
–
–
–
–
Unit
ns
ns
ns
ns
–
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