tspc860 ATMEL Corporation, tspc860 Datasheet - Page 62
tspc860
Manufacturer Part Number
tspc860
Description
Integrated Communication Processor
Manufacturer
ATMEL Corporation
Datasheet
1.TSPC860.pdf
(93 pages)
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Table 16. IDMA Controller AC Electrical Specifications
Figure 49. IDMA External Requests Timing Diagram
Figure 50. SDACK Timing Diagram – Peripheral Write, TA Sampled Low at the Falling Edge of the Clock
62
Num
40
41
42
43
44
45
46
(OUTPUT)
(OUTPUT)
(OUTPUT)
(OUTPUT)
TSPC860 [Preliminary]
RD/WR
SDACK
(OUTPUT)
CLKO
DATA
(INPUT)
Characteristic
DREQ Setup Time to Clock High
DREQ Hold Time from Clock High
SDACK Assertion Delay from Clock High
SDACK Negation Delay from Clock Low
SDACK Negation Delay from TA Low
SDACK Negation Delay from Clock High
TA Assertion to Falling Edge of the Clock Setup Time (applies to external TA)
DREQ
TS
TA
CLKO
40
42
41
43
All Frequencies
Min
7
3
–
–
–
–
7
46
Max
12
12
20
15
–
–
–
2129B–HIREL–12/04
Unit
ns
ns
ns
ns
ns
ns
ns
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