tspc860 ATMEL Corporation, tspc860 Datasheet - Page 24

• Manufacturer Part Number: tspc860
• Description: Integrated Communication Processor
• Manufacturer: ATMEL Corporation

Table 1. Signal Descriptions (Continued)
24
Power Supply
SPARE[1-4]
REJECT2
REJECT3
REJECT4
DSDO
Name
DSCK
TRST
PD[7]
RTS3
PD[6]
RTS4
PD[5]
PD[4]
PD[3]
DSDI
TCK
TMS
TDO
TDI
TSPC860 [Preliminary]
up on rev 0 to
Pulled up (Hi-
Z on rev 0 to
Hi-Z (Pulled
Pulled up
Pulled up
rev A.3)
rev A.3)
Reset
Hi-Z
Low
B7, H18,
Number
V15, H4
Figure 4
W16
V16
U15
U16
H16
G18
H17
G17
G19
T15
See
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
No-connect
Output
Power
Type
Input
Input
Input
Input
Description
General-Purpose I/O Port D Bit 7—Bit 7 of the general-purpose I/O
port D.
RTS3—Active low request to send output indicates that SCC3 is
ready to transmit data.
General-Purpose I/O Port D Bit 6—Bit 6 of the general-purpose I/O
port D.
RTS4—Active low request to send output indicates that SCC4 is
ready to transmit data.
General-Purpose I/O Port D Bit 5—Bit 5 of the general-purpose I/O
port D.
REJECT2—This input to SCC2 allows a CAM to reject the current
Ethernet frame after it determines the frame address did not match.
General-Purpose I/O Port D Bit 4—Bit 4 of the general-purpose I/O
port D.
REJECT3—This input to SCC3 allows a CAM to reject the current
Ethernet frame after it determines the frame address did not match.
General-Purpose I/O Port D Bit 3—Bit 3 of the general-purpose I/O
port D.
REJECT4—This input to SCC4 allows a CAM to reject the current
Ethernet frame after it determines the frame address did not match.
Provides clock to scan chain logic or for the development port logic.
Should be tied to Vcc if JTAG or development port are not used.
Controls the scan chain test mode operations. Should be tied to
power through a pull-up resistor if unused.
Input serial data for either the scan chain logic or the development
port and determines the operating mode of the development port at
reset.
Output serial data for either the scan chain logic or for the
development port.
Reset for the scan chain logic. If JTAG is not used, connect TRST to
ground. If JTAG is used, connect TRST to PORESET. In case
PORESET logic is powered by the keep-alive power supply
(KAPWR), connect TRST to PORESET through a diode (anode
connected to TRST and cathode to PORESET).
Spare signals—Not used on current chip revisions. Leave
unconnected.
V
V
control.
V
KAPWR—Power supply of the internal OSCM, RTC, PIT, DEC, and
TB.
V
V
DDL
DDH
DDSYN
SS
SSSYN
—Ground for circuits, except for the PLL circuitry.
—Power supply of the internal logic.
—Power supply of the I/O buffers and certain parts of the clock
, V
—Power supply of the PLL circuitry.
SSSYN1
—Ground for the PLL circuitry.
2129B–HIREL–12/04