tspc860 ATMEL Corporation, tspc860 Datasheet - Page 73

• Manufacturer Part Number: tspc860
• Description: Integrated Communication Processor
• Manufacturer: ATMEL Corporation

Figure 62. HDLC Bus Timing Diagram
Table 22. Ethernet Electrical Specifications
Notes:
2129B–HIREL–12/04
Number
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
1. The ratio SyncCLK/RCLK1 and SyncCLK/TCLK1 must be greater or equal to 2/1
2. SDACK is asserted whenever the SDMA writes the incoming frame DA into memory.
Characteristic
CLSN Width High
RCLK1 Rise/Fall Time
RCLK1 Width Low
RCLK1 Clock Period
RXD1 Setup Time
RXD1 Hold Time
RENA Active Delay (From RCLK1 Rising Edge of the Last Data Bit)
RENA Width Low
TCLK1 Rise/Fall Time
TCLK1 Width Low
TCLK1 Clock Period
TXD1 Inactive Delay (From TCLK1 Rising Edge)
TENA Active Delay (From TCLK1 Rising Edge)
TENA Inactive Delay (From TCLK1 Rising Edge)
RSTRT Active Delay (From TCLK1 Falling Edge)
RSTRT Inactive Delay (From TCLK1 Falling Edge)
REJECT Width Low
CLKO1 Low to SDACK Asserted
CLKO1 Low to SDACK Negated
TXD1 Active Delay (From TCLK1 Rising Edge)
(OUTPUT)
(OUTPUT)
INPUT)
(ECHO
TCLK1
TXD1
RTS1
CTS1
(1)
(1)
102
102
(2)
(2)
105
103
104
101
100
107
Min
100
40
40
80
20
10
40
99
10
10
10
10
10
10
–
5
–
1
–
–
All Frequencies
104
Max
120
101
15
15
50
50
50
50
50
50
20
20
–
–
–
–
–
–
–
–
Unit
CLK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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