tspc860 ATMEL Corporation, tspc860 Datasheet - Page 12

• Manufacturer Part Number: tspc860
• Description: Integrated Communication Processor
• Manufacturer: ATMEL Corporation

Table 1. Signal Descriptions (Continued)
12
CS(0-5)
CE1_B
CE2_B
Name
IRQ6
IRQ0
IRQ1
IRQ7
FRZ
CS6
CS7
BG
BB
TSPC860 [Preliminary]
States During
See Section
Hardware
Reset” on
page 27
“Signal
Reset
High
High
High
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Number
C3, A2,
D4, E4,
A4, B4
W15
V14
U14
G3
D5
C4
E2
E1
Active Pull-up
Bidirectional
Bidirectional
Bidirectional
Output
Output
Output
Type
Input
Input
Input
Description
Bus Grant—Asserted low when the arbiter of the external bus grants
the bus to a specific device. When the TSPC860 is configured to
work with the internal arbiter, BG is configured as an output and
asserted every time the external master asserts BR and its priority
request is higher than any internal sources requiring a bus transfer.
However, when the TSPC860 is configured to work with an external
arbiter, BG is an input.
Bus Busy—Asserted low by a master to show that it owns the bus.
The TSPC860 asserts BB after the arbiter grants it bus ownership
and BB is negated.
Freeze—Output asserted to indicate that the core is in debug mode.
Interrupt Request 6—One of eight external inputs that can request
(by means of the internal interrupt controller) a service routine from
the core. Note that the interrupt request signal sent to the interrupt
controller is the logical AND of FRZ/IRQ6 (if defined as IRQ6) and
DP3/IRQ6 (if defined as IRQ6).
Interrupt Request 0—One of eight external inputs that can request
(by means of the internal interrupt controller) a service routine from
the core.
Interrupt Request 1—One of eight external inputs that can request
(by means of the internal interrupt controller) a service routine from
the core.
Interrupt Request 7—One of eight external inputs that can request
(by means of the internal interrupt controller) a service routine from
the core.
Chip Select—These outputs enable peripheral or memory devices at
programmed addresses if they are appropriately defined. CS0 can
be configured to be the global chip-select for the boot device.
Chip Select 6—This output enables a peripheral or memory device
at a programmed address if defined appropriately in the BR6 and
OR6 in the memory controller.
Card Enable 1 Slot B—This output enables even byte transfers when
accesses to the PCMCIA Slot B are handled under the control of the
PCMCIA interface.
Chip Select 7—This output enables a peripheral or memory device
at a programmed address if defined appropriately in the BR7 and
OR7 in the memory controller.
Card Enable 2 Slot B—This output enables odd byte transfers when
accesses to the PCMCIA Slot B are handled under the control of the
PCMCIA interface.
2129B–HIREL–12/04