tspc860 ATMEL Corporation, tspc860 Datasheet - Page 17

• Manufacturer Part Number: tspc860
• Description: Integrated Communication Processor
• Manufacturer: ATMEL Corporation

Table 1. Signal Descriptions (Continued)
2129B–HIREL–12/04
MODCK1
MODCK2
OP(0-1)
DSDO
Name
IP_B5
IP_B6
IP_B7
LWP1
DSDI
PTR
OP2
STS
OP3
VF1
AT0
AT3
Reset
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Low
Number
L4, L2
M4
H1
K3
L1
J4
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Three-state
Three-state
Output
Type
Description
Input Port B 5—The TSPC860 monitors this input; its value and
changes are reported in the PIPR and PSCR of the PCMCIA
interface.
Load/Store Watchpoint 1—This output reports the detection of a
data watchpoint in the program flow executed by the core.
Visible Instruction Queue Flushes Status—The TSPC860 outputs
VF1 with VF0 and VF2 when instruction flow tracking is required.
VFn reports the number of instructions flushed from the instruction
queue in the core.
Input Port B 6—The TSPC860 senses this input and its value and
changes are reported in the PIPR and PSCR of the PCMCIA
interface.
Development Serial Data Input—Data input for the debug port
interface.
Address Type 0—The TSPC860 drives this bidirectional three-state
line when it initiates a transaction on the external bus. If high (1), the
transaction is the CPM. If low (0), the transaction initiator is the CPU.
This signal is not used for transactions initiated by external masters.
Input Port B 7—The TSPC860 monitors this input; its value and
changes are reported in the PIPR and PSCR of the PCMCIA
interface.
Program Trace—To allow program flow tracking, the TSPC860
asserts this output to indicate an instruction fetch is taking place.
Address Type 3—The TSPC860 drives the bidirectional three-state
signal when it starts a transaction on the external bus. When the
core initiates a transfer, AT3 indicates whether it is a reservation for a
data transfer or a program trace indication for an instruction fetch.
This signal is not used for transactions initiated by external masters.
Output Port 0-1—The TSPC860 generates these outputs as a result
of a write to the PGCRA register in the PCMCIA interface.
Output Port 2—This output is generated by the TSPC860 as a result
of a write to the PGCRB register in the PCMCIA interface.
Mode Clock 1—Input sampled when PORESET is negated to
configure PLL/clock mode.
Special Transfer Start—The TSPC860 drives this output to indicate
the start of an external bus transfer or of an internal transaction in
show-cycle mode.
Output Port 3—This output is generated by the TSPC860 as a result
of a write to the PGCRB register in the PCMCIA interface.
Mode Clock 2—This input is sampled at the PORESET negation to
configure the PLL/clock mode of operation.
Development Serial Data Output—Output data from the debug port
interface.
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