tspc860 ATMEL Corporation, tspc860 Datasheet - Page 29

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tspc860

Manufacturer Part Number
tspc860
Description
Integrated Communication Processor
Manufacturer
ATMEL Corporation
Datasheet
Package
Absolute Maximum
Ratings
Absolute Maximum Rating for the TSPC860
Table 4. Thermal Characteristics
Notes:
2129B–HIREL–12/04
Parameter
I/O Supply Voltage
Internal Supply Voltage
Backup Supply Voltage
PLL Supply Voltage
Input Voltage
Storage Temperature Range
Rating
Junction to Ambient
Junction to Board
Junction to Case
Junction to Package Top
1. Junction temperature is a function on on-chip power dissipation, package thermal resistance, mounting site (board) temper-
2. Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal.
3. Per JEDEC JESD51-6 with the board horizontal.
4. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on
5. Indicates the average thermal resistance between the die and the case top surface as measured by the cold plate method
6. Thermal characterization parameter indicating the temperature difference between package top and the junction tempera-
ature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance.
the top surface of the board near the package.
(MIL SPEC-883 Method 1012.1) with the cold plate temperature used for the case temperature. For exposed pad packages
where the pad would be expected to be soldered, junction to case thermal resistance is a simlated value from the junction to
the exposed pas without contact resistance.
ture per JEDEC JESD51-2.
(5)
(4)
(1)
(6)
Natural Convection
Air Flow (20 ft/min)
Air Flow (200 ft/min)
Natural Convection
The macrocircuits are packaged in 357-lead Plastic Ball Grid Array (BGA) packages.
The precise case outlines are described at the end of the specification.
Stresses above the absolute maximum rating may cause permanent damage to the
device. Extended operation at the maximum levels may degrade performance and affect
reliability.
Environnement
Single layer board (1s)
Four layer board (2s2p)
Single layer board (1s)
Four layer board (2s2p)
KAPWR
Symbol
V
V
V
T
DDSYN
V
DDH
STG
DDL
IN
Min
-0.3
-0.3
-0.3
-0.3
-0.3
-65
Symbol
R
R
R
R
R
R
JMA
JMA
JMA
JA
JT
JC
JB
(2)
(3)
(3)
(3)
PC860P
ZP
34
22
27
18
14
6
2
2
+150
Max
4.0
4.0
4.0
4.0
4.0
PC860P
ZQ/VR
34
22
27
18
13
8
2
3
Unit
V
V
V
V
V
C
Unit
C/W
29

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