isp1181 NXP Semiconductors, isp1181 Datasheet - Page 24

• Manufacturer Part Number: isp1181
• Description: Isp1181 Full-speed Universal Serial Bus Interface Device
• Manufacturer: NXP Semiconductors

Philips Semiconductors
12. Commands and registers
Table 14:
9397 750 08938
Product data
Name
Initialization commands
Write Control OUT Configuration
Write Control IN Configuration
Write Endpoint n Configuration
(n = 1 to 14)
Read Control OUT Configuration
Read Control IN Configuration
Read Endpoint n Configuration
(n = 1 to 14)
Write/Read Device Address
Write/Read Mode Register
Write/Read Hardware Configuration Hardware Configuration Register
Write/Read Interrupt Enable
Register
Write/Read DMA Configuration
Write/Read DMA Counter
Reset Device
Command and register summary
The functions and registers of ISP1181 are accessed via commands, which consist
of a command code followed by optional data bytes (read or write action). An
overview of the available commands and registers is given in
A complete access consists of two phases:
The following applies for register or FIFO access in 16-bit bus mode:
•
•
•
1. Command phase: when address bit A0 = 1, the ISP1181 interprets the data on
2. Data phase (optional): when address bit A0 = 0, the ISP1181 transfers the data
The upper byte (bits D15 to D8) in command phase or the undefined byte in data
phase are ignored.
The access of registers is word-aligned: byte access is not allowed.
If the packet length is odd, the upper byte of the last word in an IN endpoint buffer
is not transmitted to the host. When reading from an OUT endpoint buffer, the
upper byte of the last word must be ignored by the firmware. The packet length is
stored in the first 2 bytes of the endpoint buffer.
the lower byte of the bus (bits D7 to D0) as a command code. Commands without
a data phase are executed immediately.
on the bus to or from a register or endpoint FIFO. Multi-byte registers are
accessed least significant byte/word first.
Destination
Endpoint Configuration Register
endpoint 0 OUT
Endpoint Configuration Register
endpoint 0 IN
Endpoint Configuration Register
endpoint 1 to 14
Endpoint Configuration Register
endpoint 0 OUT
Endpoint Configuration Register
endpoint 0 IN
Endpoint Configuration Register
endpoint 1 to 14
Address Register
Mode Register
Interrupt Enable Register
DMA Configuration Register
DMA Counter Register
resets all registers
Rev. 04 — 30 October 2001
Code (Hex)
20
21
22 to 2F
30
31
32 to 3F
B6/B7
B8/B9
BA/BB
C2/C3
F0/F1
F2/F3
F6
© Koninklijke Philips Electronics N.V. 2001. All rights reserved.
Full-speed USB interface
Transaction
write 1 byte
write 1 byte
write 1 byte
read 1 byte
read 1 byte
read 1 byte
write/read 1 byte
write/read 1 byte
write/read 2 bytes
write/read 4 bytes
write/read 2 bytes
write/read 2 bytes
-
Table
14.
ISP1181
[2]
[2]
[2]
[2]
[2]
[2][3]
[1]
[2]
[2]
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