isp1181 NXP Semiconductors, isp1181 Datasheet - Page 30

• Manufacturer Part Number: isp1181
• Description: Isp1181 Full-speed Universal Serial Bus Interface Device
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Table 23:
9397 750 08938
Product data
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Interrupt Enable Register: bit allocation
reserved
IEP14
IEP6
R/W
R/W
R/W
R/W
31
23
15
0
0
0
7
0
12.1.5 Write/Read Interrupt Enable Register
Table 22:
This command is used to individually enable/disable interrupts from all endpoints, as
well as interrupts caused by events on the USB bus (SOF, SOF lost, EOT, suspend,
resume, reset). A bus reset will not change any of the programmed bit values.
The command accesses the Interrupt Enable Register, which consists of 4 bytes. The
bit allocation is given in
Code (Hex): C2/C3 — write/read Interrupt Enable Register
Transaction — write/read 4 bytes
reserved
Table 24:
Bit
2
1
0
Bit
31 to 24
23 to 10
9
8
IEP13
IEP5
R/W
R/W
R/W
R/W
30
22
14
0
0
0
6
0
Hardware Configuration Register: bit description
Interrupt Enable Register: bit description
Symbol
PWROFF
INTLVL
INTPOL
Symbol
-
IEP14 to IEP1 A logic 1 enables interrupts from the indicated endpoint.
IEP0IN
IEP0OUT
IEPSOF
IEP12
IEP4
R/W
R/W
R/W
R/W
29
21
13
0
0
0
5
0
Rev. 04 — 30 October 2001
Table
IESOF
IEP11
Description
A logic 1 enables powering-off during ‘suspend’ state. Output
SUSPEND is configured as a power switch control signal for
external devices (HIGH during ‘suspend’). This value should
always be initialized to logic 1. Bus reset value: unchanged.
Selects the interrupt signalling mode on output INT (0 = level,
1 = pulsed). In pulsed mode an interrupt produces an 166 ns
pulse. See
Selects INT signal polarity (0 = active LOW, 1 = active HIGH).
Bus reset value: unchanged.
Description
reserved; must write logic 0
A logic 1 enables interrupts from the control IN endpoint.
A logic 1 enables interrupts from the control OUT endpoint.
IEP3
R/W
R/W
R/W
R/W
28
20
12
0
0
0
4
0
23.
reserved
Section 13
IEEOT
IEP10
IEP2
R/W
R/W
R/W
R/W
27
19
11
0
0
0
3
0
for details. Bus reset value: unchanged.
IESUSP
IEP9
IEP1
R/W
R/W
R/W
R/W
26
18
10
0
0
0
2
0
© Koninklijke Philips Electronics N.V. 2001. All rights reserved.
…continued
Full-speed USB interface
IERESM
IEP0IN
IEP8
R/W
R/W
R/W
R/W
25
17
0
0
9
0
1
0
ISP1181
IEP0OUT
IERST
IEP7
R/W
R/W
R/W
R/W
24
16
0
0
8
0
0
0
30 of 71