isp1504c NXP Semiconductors, isp1504c Datasheet - Page 15

• Manufacturer Part Number: isp1504c
• Description: Ulpi Hi-speed Universal Serial Bus On-the-go Transceiver
• Manufacturer: NXP Semiconductors

NXP Semiconductors
8. Modes of operation
ISP1504A_ISP1504C_1
Product data sheet
8.1.1 Synchronous mode
8.1 ULPI modes
The ISP1504 ULPI bus can be programmed to operate in four modes. Each mode
reconfigures the signals on the data bus as described in the following subsections. Setting
more than one mode will lead to undefined behavior.
This is default mode. At power-up, and when CLOCK is stable, the ISP1504 will enter
synchronous mode. The link must synchronize all ULPI signals to CLOCK, meeting the
set-up and hold times as defined in
synchronous mode is given in
This mode is used by the link to perform the following tasks:
For more information on various synchronous mode protocols, see
Table 4.
Signal
name
CLOCK
DATA[7:0] I/O
•
•
•
•
High-speed detection handshake (chirp)
Transmit and receive USB packets
Read and write to registers
Receive USB status updates (RXCMDs)
ULPI signal description
Direction
on ISP1504
I/O
Rev. 01 — 19 October 2006
Signal description
60 MHz interface clock. If a crystal is attached or a clock is driven into
the XTAL1 pin, the ISP1504 will drive a 60 MHz output clock; otherwise,
the ISP1504 requires a 60 MHz input clock.
8-bit data bus. In synchronous mode, the link drives DATA[7:0] to LOW
by default. The link initiates transfers by sending a nonzero data pattern
called TXCMD (transmit command). In synchronous mode, the direction
of DATA[7:0] is controlled by DIR. Contents of DATA[7:0] lines must be
ignored for exactly one clock cycle whenever DIR changes value. This is
called the turnaround cycle.
Data lines have fixed direction and different meaning in low-power and
serial modes.
Table
Section
4.
15. A description of the ULPI pin behavior in
ISP1504A; ISP1504C
ULPI HS USB OTG transceiver
Section
© NXP B.V. 2006. All rights reserved.
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