isp1504c NXP Semiconductors, isp1504c Datasheet - Page 54

• Manufacturer Part Number: isp1504c
• Description: Ulpi Hi-speed Universal Serial Bus On-the-go Transceiver
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 36.
Table 37.
Table 38.
Table 39.
ISP1504A_ISP1504C_1
Product data sheet
Bit
Symbol
Reset
Access
Bit
7 to 2
1
0
Bit
7 to 0
Bit
Symbol
Reset
Access
Symbol
SCRATCH[7:0]
Debug register (address R = 15h) bit allocation
Debug register (address R = 15h) bit description
Scratch register (address R = 16h to 18h, W = 16h, S = 17h, C = 18h) bit description
Power Control register (address R = 3Dh to 3Fh, W = 3Dh, S = 3Eh, C = 3Fh) bit allocation
10.1.10 Scratch register
10.1.11 Reserved
10.1.12 Access extended register set
10.1.13 Vendor-specific registers
10.1.14 Power Control register
10.1.9 Debug register
R/W/S/C
Symbol
-
LINESTATE1
LINESTATE0
R
7
0
7
0
The bit allocation of the Debug register is given in
current value of signals useful for debugging.
This is an empty register for testing purposes; see
Registers 19h to 2Eh are not implemented. Operating on these addresses will have no
effect on the PHY.
Address 2Fh does not contain register data. Instead it links to the extended register set.
The immediate register set maps to the lower end of the extended register set.
Addresses 30h to 3Fh contains vendor-specific registers.
This register controls various aspects of the ISP1504.
the register.
Access
R/W/S/C
R/W/S/C
R
6
0
6
0
reserved
Description
reserved
Line State 1: Contains the current value of LINESTATE 1.
Line State 0: Contains the current value of LINESTATE 0.
R/W/S/C
Value
00h
R
5
0
5
0
Rev. 01 — 19 October 2006
reserved
Description
Scratch: This is an empty register byte for testing purposes.
Software can read, write, set and clear this register; and the
functionality of the PHY will not be affected.
R/W/S/C
R
4
0
4
0
BVALID_
R/W/S/C
FALL
R
3
0
3
0
ISP1504A; ISP1504C
Table
Table
Table 39
BVALID_
R/W/S/C
RISE
36. This register indicates the
38.
ULPI HS USB OTG transceiver
R
2
0
2
0
shows the bit allocation of
R/W/S/C
STATE1
LINE
R
1
0
1
0
© NXP B.V. 2006. All rights reserved.
reserved
R/W/S/C
STATE0
LINE
R
0
0
0
0
54 of 84