isp1504c NXP Semiconductors, isp1504c Datasheet - Page 80

• Manufacturer Part Number: isp1504c
• Description: Ulpi Hi-speed Universal Serial Bus On-the-go Transceiver
• Manufacturer: NXP Semiconductors

NXP Semiconductors
24. Tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10. TXCMD byte format . . . . . . . . . . . . . . . . . . . . .26
Table 11. RXCMD byte format . . . . . . . . . . . . . . . . . . . . .27
Table 12. LINESTATE[1:0] encoding for upstream facing
Table 13. LINESTATE[1:0] encoding for downstream facing
Table 14. V
Table 15. PHY pipeline delays . . . . . . . . . . . . . . . . . . . . .34
Table 16. Link decision times . . . . . . . . . . . . . . . . . . . . .35
Table 17. Register map overview . . . . . . . . . . . . . . . . . .47
Table 18. Vendor ID Low register (address R = 00h) bit
Table 19. Vendor ID High register (address R = 01h) bit
Table 20. Product ID Low register (address R = 02h) bit
Table 21. Product ID High register (address R = 03h) bit
Table 22. Function Control register (address R =
Table 23. Function Control register (address R
Table 24. Interface Control register (address R =
Table 25. Interface Control register (address R =
Table 26. OTG Control register (address R = 0Ah to 0Ch,
Table 27. OTG Control register (address R = 0Ah to 0Ch,
Table 28. USB Interrupt Enable Rising Edge register
ISP1504A_ISP1504C_1
Product data sheet
Ordering information . . . . . . . . . . . . . . . . . . . . .3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .5
Recommended charge pump capacitor value .12
ULPI signal description . . . . . . . . . . . . . . . . . .15
Signal mapping during low-power mode . . . . .16
Signal mapping for 6-pin serial mode . . . . . . .17
Signal mapping for 3-pin serial mode . . . . . . .18
Operating states and their corresponding resistor
settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
OTG Control register power control bits . . . . .25
ports: peripheral . . . . . . . . . . . . . . . . . . . . . . . .28
ports: host . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
applications . . . . . . . . . . . . . . . . . . . . . . . . . . .29
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
04h to 06h, W = 04h, S = 05h, C = 06h) bit
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
= 04h to 06h, W = 04h, S = 05h, C = 06h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
07h to 09h, W = 07h, S = 08h, C = 09h) bit
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
07h to 09h, W = 07h, S = 08h, C = 09h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
W = 0Ah, S = 0Bh, C = 0Ch) bit allocation . . .50
W = 0Ah, S = 0Bh, C = 0Ch) bit description . .51
(address R = 0Dh to 0Fh, W = 0Dh, S = 0Eh, C =
0Fh) bit allocation . . . . . . . . . . . . . . . . . . . . . .51
BUS
indicators in RXCMD required for typical
Rev. 01 — 19 October 2006
Table 29. USB Interrupt Enable Rising Edge register
Table 30. USB Interrupt Enable Falling Edge register
Table 31. USB Interrupt Enable Falling Edge register
Table 32. USB Interrupt Status register (address R = 13h)
Table 33. USB Interrupt Status register (address R = 13h)
Table 34. USB Interrupt Latch register (address R = 14h) bit
Table 35. USB Interrupt Latch register (address R = 14h) bit
Table 36. Debug register (address R = 15h) bit allocation .
Table 37. Debug register (address R = 15h) bit
Table 38. Scratch register (address R = 16h to 18h, W =
Table 39. Power Control register (address R = 3Dh to 3Fh,
Table 40. Power Control register (address R = 3Dh to 3Fh,
Table 41. Limiting values . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 42. Recommended operating conditions . . . . . . . . 57
Table 43. Static characteristics: supply pins . . . . . . . . . . 58
Table 44. Static characteristics: digital pins (CLOCK, DIR,
Table 45. Static characteristics: digital pin FAULT . . . . . 59
Table 46. Static characteristics: digital pin PSW_N . . . . 59
Table 47. Static characteristics: analog I/O pins
Table 48. Static characteristics: charge pump . . . . . . . . 61
Table 49. Static characteristics: V
Table 50. Static characteristics: V
Table 51. Static characteristics: ID detection circuit . . . . 62
Table 52. Static characteristics: resistor reference . . . . . 62
Table 53. Dynamic characteristics: reset and clock . . . . 64
Table 54. Dynamic characteristics: digital I/O pins . . . . . 65
Table 55. Dynamic characteristics: analog I/O pins (DP and
Table 56. Recommended bill of materials . . . . . . . . . . . . 69
Table 57. SnPb eutectic process (from J-STD-020C) . . . 76
(address R = 0Dh to 0Fh, W = 0Dh, S = 0Eh, C =
0Fh) bit description . . . . . . . . . . . . . . . . . . . . . 52
(address R = 10h to 12h, W = 10h, S = 11h, C =
12h) bit allocation . . . . . . . . . . . . . . . . . . . . . . 52
(address R = 10h to 12h, W = 10h, S = 11h, C =
12h) bit description . . . . . . . . . . . . . . . . . . . . . 52
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . 53
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 53
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
54
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
16h, S = 17h, C = 18h) bit description . . . . . . . 54
W = 3Dh, S = 3Eh, C = 3Fh) bit allocation . . . 54
W = 3Dh, S = 3Eh, C = 3Fh) bit description . . 55
STP, NXT, DATA[7:0], RESET_N,
CHIP_SELECT_N) . . . . . . . . . . . . . . . . . . . . . 58
(DP, DM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
DM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
ISP1504A; ISP1504C
ULPI HS USB OTG transceiver
BUS
BUS
comparators . . . . 61
resistors . . . . . . . . 62
© NXP B.V. 2006. All rights reserved.
continued >>
80 of 84