isp1564 NXP Semiconductors, isp1564 Datasheet - Page 21

• Manufacturer Part Number: isp1564
• Description: Isp1564 Hi-speed Universal Serial Bus Pci Host Controller
• Manufacturer: NXP Semiconductors

NXP Semiconductors
Table 19.
Legend: * reset value
[1]
Table 20.
Legend: * reset value
Table 21.
Legend: * reset value
Table 22.
Legend: * reset value
ISP1564_1
Product data sheet
Bit
15 to 0
Bit
7 to 0
Bit
7 to 0
Bit
7 to 0
X is 1h for OHCI; X is 2h for EHCI.
Symbol
CP[7:0]
Symbol
IL[7:0]
Symbol
IP[7:0]
SID - Subsystem ID register (address 2Eh) bit description
CP - Capabilities Pointer register (address 34h) bit description
IL - Interrupt Line register (address 3Ch) bit description
IP - Interrupt Pin register (address 3Dh) bit description
Symbol
SID[15:0]
8.2.1.13 Capabilities Pointer register
8.2.1.14 Interrupt Line register
8.2.1.15 Interrupt Pin register
Access Value
R/W
Access
R
Access
R
This register is used to point to a linked list of new capabilities implemented by the device.
This register is only valid if CL (bit 4 in the Status register) is set. If implemented, bit 1 and
bit 0 are reserved and must be set to 00b. Software must mask these bits off before using
this register as a pointer in configuration space to the first entry of a linked list of new
capabilities. The bit description of the register is given in
This is a 1-byte register used to communicate interrupt line routing information. This
register must be implemented by any device or device function that uses an interrupt pin.
The interrupt allocation is done by the BIOS. The POST software needs to write the
routing information to this register because it initializes and configures the system.
The value in this register specifies which input of the system interrupt controller(s) the
interrupt pin of the device is connected. This value is used by device drivers and operating
systems to determine priority and vector information. Values in this register are system
architecture specific. The bit description of the register is given in
This 1-byte register is use to specify which interrupt pin the device or device function uses.
A value of 1h corresponds to INTA#, 2h corresponds to INTB#, 3h corresponds to INTC#,
and 4h corresponds to INTD#. Devices or functions that do not use the interrupt pin must
set this register to logic 0. The bit description is given in
Access
R
00h*
Value
DCh*
Value
01h*
Value
156Xh*
Description
Interrupt Line: Indicates which IRQ is used to report interrupt from the ISP1564.
[1]
Description
Capabilities Pointer: EHCI efficiently manages power using this register. This
Power Management register is allocated at offset DCh. Only one Host
Controller is needed to manage power in the ISP1564.
Description
Interrupt Pin: INTA# is the default interrupt pin used by the ISP1564.
Rev. 01 — 4 December 2006
Description
Subsystem ID: For the ISP1564, NXP Semiconductors has defined OHCI
functions as 1561h, and the EHCI function as 1562h.
Table
Table
HS USB PCI Host Controller
22.
20.
Table
© NXP B.V. 2006. All rights reserved.
21.
ISP1564
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